Abstract: The inventive method provides for a method of p-type doping of Ga2O3 without adding impurity elements. Embodiments allow for significant simplification relative to extrinsic impurity element doping, and thus offers a reduced fabrication cost while being more temperature resistant since the defect dopants require higher temperatures to alter their impact. Certain methods disclosed provide for p-type gallium oxide formation via intrinsic defect doping, without requiring the addition of impurity elements which provide significant simplification relative to the existing state of the art approaches providing more temperature and radiation resistance, while offering a reduced fabrication cost.

Abstract: In one aspect, metal oxide compositions having electronic structure of multiple band gaps are described. In some embodiments, a metal oxide composition comprises a (Co,Ni)O alloy having electronic structure including multiple band gaps. The (Co,Ni)O alloy can include a first band gap and a second band gap, the first band gap separating valence and conduction bands of the electronic structure.

Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.

Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.

Abstract: A nitride-based semiconductor light-emitting element LE1 or LD1 has: a gallium nitride substrate 11 having a principal surface 11a which makes an angle ?, in the range 40° to 50° or in the range more than 90° to 130°, with the reference plane Sc perpendicular to the reference axis Cx extending in the c axis direction; an n-type gallium nitride-based semiconductor layer 13; a second gallium nitride-based semiconductor layer 17; and a light-emitting layer 15 including a plurality of well layers of InGaN and a plurality of barrier layers 23 of a GaN-based semiconductor, wherein the direction of piezoelectric polarization of the plurality of well layers 21 is the direction from the n-type gallium nitride-based semiconductor layer 13 toward the second gallium nitride-based semiconductor layer 17.

Abstract: A method for producing a group 3-5 nitride semiconductor includes the steps of (i), (ii), (iii) in this order: (i) placing inorganic particles on a substrate, (ii) epitaxially growing a semiconductor layer by using the inorganic particles as a mask, and (iii) separating the substrate and the semiconductor layer by irradiating the interface between the substrate and the semiconductor layer with light; and a method for producing a light emitting device further includes adding electrodes.

Abstract: A nitride-based semiconductor light-emitting element LE1 or LD1 has: a gallium nitride substrate 11 having a principal surface 11a which makes an angle ?, in the range 40° to 50° or in the range more than 90° to 130°, with the reference plane Sc perpendicular to the reference axis Cx extending in the c axis direction; an n-type gallium nitride-based semiconductor layer 13; a second gallium nitride-based semiconductor layer 17; and a light-emitting layer 15 including a plurality of well layers of InGaN and a plurality of barrier layers 23 of a GaN-based semiconductor, wherein the direction of piezoelectric polarization of the plurality of well layers 21 is the direction from the n-type gallium nitride-based semiconductor layer 13 toward the second gallium nitride-based semiconductor layer 17.

Abstract: A film deposition method including: a step of carrying a substrate into a vacuum chamber, and placing the substrate on a turntable; a step of rotating the turntable; and an adsorption-formation-irradiation step of supplying a first reaction gas to the substrate from a first reaction gas supply part to adsorb the first reaction gas on the substrate; supplying a second reaction gas from a second reaction gas supply part so that the first reaction gas adsorbed on the substrate reacts with the second reaction gas so as to form a reaction product on the substrate; and supplying a hydrogen containing gas to a plasma generation part that is separated from the first reaction gas supply part and the second reaction gas supply part in a circumferential direction of the turntable so as to generate plasma above the turntable and to irradiate the plasma to the reaction product.

Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.

Abstract: It is an object of the present invention to stably form an N-doped ZnO-based compound thin film. In the present invention, a gas containing oxygen and nitrogen and a nitrogen gas together with an organometallic material gas are supplied into a low-electron-temperature high-density plasma which is excited by microwave, thereby forming the N-doped ZnO-based compound thin film on a substrate as a film forming object.

Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {1011} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {1013} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {1122} gallium nitride (GaN) grown on a {1100} sapphire substrate, and (4) {1013} gallium nitride (GaN) grown on a {1100} sapphire substrate.

Abstract: An improved feeder system and method for vapor transport deposition that includes at least two vaporizers couple to a common distributor for vaporizing and co-depositing at least any two vaporizable materials as a material layer on a substrate. Composition of the material layer can be controlled by changing the flow of vapors from the respective vaporizers into the distributor to adjust the proportion of respective vapors in the combined vapor prior to deposition. Flow of the vapors from the respective vaporizers into the distributor may be controlled by adjusting the flow of carrier gas transporting the raw material into the vaporizer and/or by adjusting the vibration speed and/or amplitude of the powder feeders that process the raw material.

Abstract: A light-emitting diode includes an n-type nitride semiconductor layer, a multiple quantum well, a p-type nitride semiconductor layer, a window electrode layer, a p-side electrode, and an n-side electrode, which are stacked in this order. The window electrode layer comprises an n-type single-crystalline ITO transparent film and an n-type single-crystalline ZnO transparent film. The p-type nitride semiconductor layer is in contact with the n-type single-crystalline ITO transparent film, the n-type single-crystalline ITO transparent film is in contact with the n-type single-crystalline ZnO transparent film, and the p-side electrode is in connected with the n-type single-crystalline ZnO transparent film. The n-type single-crystalline ITO transparent film contains Ga, a molar ratio of Ga/(In+Ga) being not less than 0.08 and not more than 0.5. Thickness of the n-type single-crystalline ITO transparent film is not less than 1.1 nm and not more than 55 nm.

Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

Abstract: It is an object of the present invention to stably form an N-doped ZnO-based compound thin film. In the present invention, a gas containing oxygen and nitrogen and a nitrogen gas together with an organometallic material gas are supplied into a low-electron-temperature high-density plasma which is excited by microwave, thereby forming the N-doped ZnO-based compound thin film on a substrate as a film forming object.

Abstract: A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: A method for fabricating a copper indium diselenide semiconductor film using a self cleaning furnace is provided. The method includes transferring a plurality of substrates having a copper and indium composite structure into a furnace comprising a processing region and at least one end cap region disengageably coupled to the processing region. The method also includes introducing a gaseous species including a hydrogen species and a selenium species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature to initiate formation of a copper indium diselenide film on each of the substrates. The method further includes decomposing residual selenide species from an inner region of the process region of the furnace. The method further includes depositing elemental selenium species within a vicinity of the end cap region operable at a third temperature.

Abstract: Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate into a chamber; injecting a Zn precursor and an oxygen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the oxygen precursor using an atomic layer deposition (ALD) technique to form a ZnO thin layer on the substrate; and injecting a Zn precursor and an nitrogen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the nitrogen precursor to form a doping layer on the ZnO thin layer.

Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.

Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {10 13 } gallium nitride (GaN) grown on a {110} spinel substrate, (3) {11 22} gallium nitride (GaN) grown on a {1 100} sapphire substrate, and (4) {10 13} gallium nitride (GaN) grown on a {1 100} sapphire substrate.

Abstract: Provided are a Thin Film Transistor (TFT) and a method of manufacturing the same. The TFT includes a gate electrode; a source electrode and a drain electrode spaced from the gate electrode in a vertical direction and spaced from each other in a horizontal direction; a gate insulation layer disposed between the gate electrode and the source and drain electrodes; and an active layer disposed between the gate insulation layer and the source and drain electrodes. The active layer is formed of a conductive oxide layer and comprises at least two layers having different conductivities according to an impurity doped into the conductive oxide layer.

Abstract: The invention can provide or facilitate energy recovery operations during semiconductor processing operations by utilizing a bell jar having a radiation shield thereon that is comprised of a mediating layer comprising nickel disposed on an interior surface of the bell jar, and a reflective layer which can comprise a gold layer that is disposed on the mediating layer. The reflective layer has an emissivity of less than 5% and, more preferably, the reflective layer has an emissivity of less than about 1%. Heat from the reaction chamber can be used to reduce the heating load of one or more other unit operations.

Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

Abstract: A multilayer film stack containing germanium, antimony and tellurium that can be annealed to form a GST product material of homogeneous and smooth character, wherein at least one antimony-containing layer is isolated from a tellurium-containing layer by an intervening germanium layer, and the multilayer film stack comprises at least two intervening germanium layers. The multilayer film stack can be formed by vapor deposition techniques such as chemical vapor deposition or atomic layer deposition. The annealable multilayer film stack can be formed in high aspect ratio vias to form phase change memory devices of superior character with respect to the stoichiometric and morphological characteristics of the GST product material.

Abstract: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses applied larger when growing a nitride semiconductor film on the base substrate from a central portion of the base substrate towards a peripheral portion. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion.

Abstract: To provide a manufacturing method for an epitaxial wafer that alleviates distortions on a back surface thereof due to sticking between a wafer and a susceptor, thereby preventing decrease in flatness thereof due to a lift pin. A manufacturing method for an epitaxial wafer according to the present invention includes: an oxide film forming step in which an oxide film is formed on a back surface thereof; an etching step in which a hydrophobic portion exposing a back surface of the semiconductor wafer is provided by partially removing the oxide film; a wafer placing step in which the semiconductor wafer is placed; and an epitaxial growth step in which an epitaxial layer is grown on a main surface of the semiconductor wafer; and the diameter of the lift pin installation circle provided on a circle on a bottom face of a susceptor is smaller than that of the hydrophobic portion.

Abstract: The present invention discloses a method for fabricating a nanoscale thermoelectric device, which comprises steps: providing at least one template having a group of nanoscale pores; forming a substrate on the bottom of the template; injecting a molten semiconductor material into the nanoscale pores to form a group of semiconductor nanoscale wires; removing the substrate to obtain a semiconductor nanoscale wire array; and using metallic conductors to cascade at least two semiconductor nanoscale wire arrays to form a thermoelectric device having a higher thermoelectric conversion efficiency.

Abstract: Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate into a chamber; injecting a Zn precursor and an oxygen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the oxygen precursor using an atomic layer deposition (ALD) technique to form a ZnO thin layer on the substrate; and injecting a Zn precursor and an nitrogen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the nitrogen precursor to form a doping layer on the ZnO thin layer.

Abstract: The present invention provides metal precursors for low temperature deposition. The metal precursors include a metal ring compound including at least one metal as one of a plurality of elements forming a ring. Methods of forming a metal thin layer and manufacturing a phase change memory device including use of the metal precursors is also provided.

Abstract: An oxide semiconductor target of a ZTO (zinc tin complex oxide) type oxide semiconductor material of an appropriate (Zn/(Zn+Sn)) composition having high mobility and threshold potential stability and with less restriction in view of the cost and the resource and with less restriction in view of the process, and an oxide semiconductor device using the same, in which a sintered Zn tin complex oxide with a (Zn/(Zn+Sn)) composition of 0.6 to 0.8 is used as a target, the resistivity of the target itself is at a high resistance of 1 ?cm or higher and, further, the total concentration of impurities is controlled to 100 ppm or less.

Abstract: A method of synthesizing electronic components incorporating nanoscale filamentary structures in which method a metallic catalyst is deposited in a nanoporous membrane , the catalyst being adapted to penetrate in at least some of the pores of the nanoporous membrane , and filamentary structures are grown on the catalyst in at least some of the pores in the nanoporous membrane . The nanoporous membrane is prepared in a manner suitable for ensuring that the wall of the pores include a single-crystal zone, and at least part of the catalyst is grown epitaxially on said single-crystal zone.

Abstract: In a method for producing epitaxially coated semiconductor wafers, a multiplicity of prepared, front side-polished semiconductor wafers are successively coated individually with an epitaxial layer on their polished front sides at temperatures of 800-1200° C. in a reactor, while supporting the prepared semiconductor wafer over a susceptor having a gas-permeable structure, on a ring placed on the susceptor which acts as a thermal buffer between the susceptor and the supported semiconductor wafer, the semiconductor wafer resting on the ring, and its backside facing but not contacting the susceptor, so that gaseous substances are delivered from a region over the backside of the semiconductor wafer by gas diffusion through the susceptor into a region over the backside of the susceptor, the semiconductor wafer contacting the ring only in an edge region of its backside, wherein no stresses measurable by means of photoelastic stress measurement (“SIRD”) occur in the semiconductor wafer.

Abstract: A method is provided for fabricating a thin-film semiconductor device. The method includes providing a plurality of raw semiconductor materials. The raw semiconductor materials undergo a pre-reacting process to form a homogeneous compound semiconductor material. This pre-reaction typically includes processing above the liquidus temperature of the compound semiconductor. The compound semiconductor material is reduced to a particulate form and deposited onto a substrate to form a thin-film having a composition and atomic structure substantially the same as a composition and atomic structure of the compound semiconductor material.

Abstract: The invention relates to a device for depositing one or more layers, in particular crystalline layers, on one or more substrates, in particular crystalline substrates (6), which are situated on a susceptor (3) in a process chamber (2) of a reactor (1). A process chamber wall (4) that can be actively heated by a process chamber heating unit (11) lies opposite the susceptor (3) that can be actively heated by the susceptor heating unit (11). The device is provided with a gas inlet organ (7) for introducing process gases into the process chamber and the process chamber heating unit (11) has a coolant channel (13) and is situated at a distance from the exterior (18) of the process chamber wall (4) during the active heating of the latter (4). The aim of the invention is to also allow the device to be used with hybrid technology.

Abstract: A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination.

Abstract: A semiconductor device includes: a semiconductor substrate having a first semiconductor layer, an insulation layer and a second semiconductor layer, which are stacked in this order; a LDMOS transistor disposed on the first semiconductor layer; and a region having a dielectric constant, which is lower than that of the first or second semiconductor layer. The region contacts the insulation layer, and the region is disposed between a source and a drain of the LDMOS transistor. The device has high withstand voltage in a direction perpendicular to the substrate.

Abstract: An apparatus designed to increase the quality of a low-resistance semiconductor single crystal doped with an N-type volatile dopant to a high concentration and increase the production yield by controlling the pressure inside the furnace with good controllability. A vacuum line, a pressure control valve, and an open valve are newly added to the conventional semiconductor single crystal production apparatus. A controller controls the pressure control valve on the basis of a detection value of pressure detection means so as to obtain the desired low resistance value of the semiconductor single crystal. The open valve is controlled so that the open valve is opened in a case where the pressure inside the furnace detected by the pressure detection means reaches an abnormal value.

Abstract: Si atoms obtained by thermal decomposition of SiH4 are adsorbed in advance on one surface of a semiconductor substrate and side surfaces of a semiconductor mesa part. Thereby, prior to the growth of a buried layer, a diffusion protection layer composed of Si-doped InP with high impurity concentration is formed. As a result, when the buried layer is grown, Zn diffusing from an upper cladding layer is trapped by the diffusion protection layer, and interdiffusion between Zn and Fe is inhibited. Since the diffusion protection layer is formed uniformly at a small thickness of several monolayers, the diffusion protection layer is also inhibited from becoming a current leakage path. Consequently, the reliability of the semiconductor optical device can be improved.

Abstract: A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber.

Abstract: To provide a manufacturing method for an epitaxial wafer that alleviates distortions on a back surface thereof due to sticking between a wafer and a susceptor, thereby preventing decrease in flatness thereof due to a lift pin. A manufacturing method for an epitaxial wafer according to the present invention includes: an oxide film forming step in which an oxide film is formed on a back surface thereof; an etching step in which a hydrophobic portion exposing a back surface of the semiconductor wafer is provided by partially removing the oxide film; a wafer placing step in which the semiconductor wafer is placed; and an epitaxial growth step in which an epitaxial layer is grown on a main surface of the semiconductor wafer; and the diameter of the lift pin installation circle provided on a circle on a bottom face of a susceptor is smaller than that of the hydrophobic portion.

Abstract: Hybrid chemical vapor deposition systems for depositing a semiconductor-containing thin film over a substrate comprise a reaction space, a substrate support member configured to permit movement of a substrate in a longitudinal direction and a plasma-generating apparatus disposed in the reaction space and configured to form plasma-excited species of a vapor phase chemical. The systems further comprise a hot wire unit disposed in the reaction space and configured to heat and decompose a vapor phase chemical. The hot wire unit can be a filament. The systems can further comprise an additional reaction space proximate the reaction space. The additional reaction space can comprise a plasma-generating apparatus configured to form plasma-excited species of a vapor phase chemical and a hot wire unit configured to heat and decompose a vapor phase chemical.

Abstract: A semiconductor device manufacturing method comprises the steps of loading a substrate into a processing chamber, mounting the substrate on a support tool in the processing chamber, processing the substrate mounted on the support tool by supplying process gas into the processing chamber, purging the interior of the processing chamber after the substrate processing step, and unloading the processed substrate from the processing chamber after the step of purging the interior of the processing chamber, wherein in the step of purging the interior of the processing chamber, exhaust is performed toward above the substrate and toward below the substrate in the processing chamber, and the exhaust rate toward above the substrate is set larger than the exhaust rate toward below the substrate.

Abstract: A method for forming a film on a substrate comprising: heating a solid organosilane source in a heating chamber to form a gaseous precursor; transferring the gaseous precursor to a deposition chamber; and reacting the gaseous precursor using an energy source to form the film on the substrate. The film comprises Si and C, and optionally comprises other elements such as N, O, F, B, P, or a combination thereof.

Abstract: A method of manufacturing a semiconductor device includes: forming an oxide film having a predetermined film thickness on a substrate by repeating a process of forming a predetermined element-containing layer on the substrate by supplying source gas containing a predetermined element into a process vessel accommodating the substrate, and a process of changing the predetermined element-containing layer to an oxide layer by supplying oxygen-containing gas and hydrogen-containing gas into the process vessel that is set below atmospheric pressure, wherein the oxygen-containing gas is oxygen gas or ozone gas, the hydrogen-containing gas is hydrogen gas or deuterium gas, and the temperature of the substrate is in a range from 400° C. or more to 700° C. or less in the process of forming the oxide film.

Abstract: Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web.

Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1?xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1?xN nucleation layer, and cooling the substrate under a nitrogen overpressure.

Abstract: A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al,In,Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.

Abstract: This invention relates to a method for producing group IB-IIA-VIA quaternary or higher alloy semiconductor films wherein the method comprises the steps of (i) providing a metal film comprising a mixture of group IB and group IIIA metals; (ii) heat treating the metal film in the presence of a source of a first group VIA element (said first group VIA element hereinafter being referred to as VIA1) under conditions to form a first film comprising a mixture of at least one binary alloy selected from the group consisting of a group IB-VIA1 alloy and a group IIIA-VIA1 alloy and at least one group IB-IIIA-VIA1 ternary alloy (iii) optionally heat treating the first film in the presence of a source of a second group VIA element (said second group VI element hereinafter being referred to as VIA2) under conditions to convert the first film into a second film comprising at least one alloy selected from the group consisting of a group IB-VIA1-VIA2 alloy and a group IIIA-VIA1-VIA2 alloy; and the at least one group IB-III-VI

Abstract: A vapor growth apparatus forming a film on a substrate using a first source gas and a second source gas different form the first source gas, includes: a reaction chamber in which the substrate is disposed; a first source gas introduction path that communicates with the reaction chamber and introduces the first source gas; a second source gas introduction path that communicates with the reaction chamber and introduces the second source gas; and a separation gas introduction path that communicates with the reaction chamber between the first source gas introduction path and the second source gas introduction path and introduces a separation gas. The separation gas has a reaction rate with the first source gas and a reaction rate with the second source gas lower than the reaction rate between the first source gas and the second source gas.

Abstract: There are provided a substrate processing method and apparatus adapted to prevent deterioration of film thickness uniformity while maintaining the film forming rate. The substrate processing method comprises: (a) accommodating a plurality of substrates in a process chamber by carrying and stacking the substrates in the process chamber, (b) forming first amorphous silicon films to a predetermined thickness by heating at least the substrates and supplying first gas, and (c) forming second amorphous silicon films to a predetermined thickness by heating at least the substrates and supplying second gas different from the first gas. The first gas is higher order gas than the second gas.