Alloying Of Impurity Material, E.g., Dopant, Electrode Material, With Semiconductor Body (epo) Patents (Class 257/E21.47)
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Patent number: 8901010Abstract: Methods for protecting a texturized region and a lightly doped diffusion region of a solar cell to improve solar cell lifetime and efficiency are disclosed. In an embodiment, an example method includes providing a solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, a silicon substrate and where the silicon substrate includes a texturized region and a lightly doped diffusion region. The method includes placing the solar cell on a receiving medium with the front side of the solar cell placed on an upper surface of the receiving medium, where the upper surface of the receiving medium prevents damage to the to the lightly doped diffusion region and damage to the texturized region on the front side of the solar cell during a contact printing process or transferring. In an embodiment, the lightly doped diffusion region has a doping concentration below 1×1019 cm?3 and the receiving medium includes a material having a moh's hardness in the range of 5-10.Type: GrantFiled: March 15, 2013Date of Patent: December 2, 2014Assignee: SunPower CorporationInventors: Staffan Westerberg, Florito Dennis Tingchuy Vicente, Michael Cudzinovic, Princess Carmi Tomada, Jemellee Guiao
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Patent number: 8546247Abstract: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.Type: GrantFiled: February 2, 2009Date of Patent: October 1, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Hidenobu Fukutome, Youichi Momiyama
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Patent number: 8395183Abstract: Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer to surround the fluorescent layer; and a lens disposed on the light emitting device and supported by the substrate, wherein the lens includes a lens body having a first recess formed at a center of a top surface of the lens body and a second recess formed at a center of a bottom surface of the lens body, and a lens supporter provided at the bottom surface of the lens body to support the lens body such that the lens body is spaced apart from the substrate.Type: GrantFiled: November 19, 2010Date of Patent: March 12, 2013Assignee: LG Innotek Co., Ltd.Inventors: Sang Won Lee, Gyu Hyeong Bak
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Patent number: 8058159Abstract: A method for fabricating a component is disclosed. The method includes: providing a member having an effective work function of an initial value, disposing a sacrificial layer on a surface of the member, disposing a first agent within the member to obtain a predetermined concentration of the agent at said surface of the member, annealing the member, and removing the sacrificial layer to expose said surface of the member, wherein said surface has a post-process effective work function that is different from the initial value.Type: GrantFiled: August 27, 2008Date of Patent: November 15, 2011Assignee: General Electric CompanyInventors: Vance Robinson, Stanton Earl Weaver, Joseph Darryl Michael
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Publication number: 20110272744Abstract: Described herein are semiconductor structures comprising laterally varying II-VI alloy layer formed over a surface of a substrate. Further, methods are provided for preparing laterally varying II-VI alloy layers over at least a portion of a surface of a substrate comprising contacting at least a portion of a surface of a substrate within a reaction zone with a chemical vapor under suitable reaction conditions to form a laterally varying II-VI alloy layer over the portion of the surface of the substrate, wherein the chemical vapor is generated by heating at least two II-VI binary compounds; and the reaction zone has a temperature gradient of at least 50-100° C. along an extent of the reaction zone. Also described here are devices such as lasers, light emitting diodes, detectors, or solar cells that can use such semiconductor structures.Type: ApplicationFiled: November 6, 2009Publication date: November 10, 2011Applicant: ARIZONA BOARD OF REGENTS, a body corporate acting for and on behalf of ARIZONA STATE UNIVERSITYInventors: Cun-zheng Ning, Anlian Pan
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Patent number: 8030716Abstract: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.Type: GrantFiled: September 16, 2010Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P. Chudzik, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7863126Abstract: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.Type: GrantFiled: May 15, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P. Chudzik, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20100320456Abstract: The present invention is directed to methods for depositing doped and/or alloyed semiconductor layers, an apparatus suitable for the depositing, and products prepared therefrom.Type: ApplicationFiled: June 19, 2009Publication date: December 23, 2010Applicant: EPV Solar, Inc.Inventors: Alan E. DELAHOY, Gaurav SARAF, Sheyu GUO
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Patent number: 7838906Abstract: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder than the substrate 2, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating film 12S provided on a side surface of the semiconductor layer 4.Type: GrantFiled: October 3, 2008Date of Patent: November 23, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Ken Sato, Nobuo Kaneko
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Publication number: 20100180950Abstract: A method and corresponding system for providing a uniform nanowire array including uniform nanowires composed of at least three elements is presented. An embodiment of the method includes growing an array of two-element nanowires, and thereafter uniformly doping or alloying each two-element nanowire, with respect to each other two-element nanowire, with at least one doping or alloying element through a wet chemical synthesis with a precursor solution, to produce the uniform array of nanowires composed of at least three elements. The two-element nanowire can include Zn and O, and the at least one doping or alloying element can be Mg, Cd, Mn, Cu, Be, Fe, and Co. Applications of the three-element nanowire array include solar cells and light emitting diodes with improved efficiencies over existing technologies.Type: ApplicationFiled: November 13, 2009Publication date: July 22, 2010Applicant: University of ConnecticutInventors: Pu-Xian Gao, Paresh Shimpi
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Patent number: 7645652Abstract: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: a semiconductor substrate of a first conductivity type having a photodiode region and a transistor region defined therein; a gate electrode formed above the transistor region of the semiconductor substrate with a gate insulating layer interposed therebetween; a first impurity region formed of the first conductivity type in the semiconductor substrate below the gate electrode and having a higher concentration of first conductivity type ions than the semiconductor substrate; and a second impurity region formed of a second conductivity type in the photodiode region of the semiconductor substrate.Type: GrantFiled: August 21, 2006Date of Patent: January 12, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Lim Keun Hyuk
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Patent number: 7618884Abstract: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.Type: GrantFiled: April 21, 2008Date of Patent: November 17, 2009Assignee: Fairchild Semiconductor CorporationInventors: William F. Seng, Richard L. Woodin, Carl Anthony Witt
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Publication number: 20090085211Abstract: Embodiments of the invention describe electrical contacts for integrated circuits and methods of forming using gas cluster ion beam (GCIB) processing. The electrical contacts contain a fused metal-containing layer formed by exposing a patterned structure to a gas cluster ion beam containing a transition metal precursor or a rare earth metal precursor.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Rodney L. Robison, Douglas Trickett
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Patent number: 7268073Abstract: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as to inhibit corrosion of the copper structure (26). All or a portion of the corrosion protection layer (30) is then removed (214) in forming an opening in an overlying dielectric (44) in a subsequent interconnect layer.Type: GrantFiled: November 10, 2004Date of Patent: September 11, 2007Assignee: Texas Instruments IncorporatedInventors: Deepak A. Ramappa, Mona Eissa, Christopher Lyle Borst, Ting Y. Tsui
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Patent number: 7084052Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.Type: GrantFiled: August 13, 2004Date of Patent: August 1, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Kiichi Hirano, Naoya Sotani, Toshifumi Yamaji, Yoshihiro Morimoto, Kiyoshi Yoneda