Deposition Of Conductive Or Insulating Materials For Electrode (epo) Patents (Class 257/E21.477)
-
Publication number: 20090160008Abstract: A semiconductor device that includes an n-type semiconductor substrate and an upper electrode formed on an upper face of the semiconductor substrate and a method of manufacturing the semiconductor device are provided. A p-type semiconductor region is repeatedly formed in the semiconductor substrate in at least one direction parallel to the substrate plane so as to be exposed on an upper face of the semiconductor substrate. The upper electrode includes a metal electrode portion; and a semiconductor electrode portion made of a semiconductor material whose band gap is narrower than that of the semiconductor substrate. The semiconductor electrode portion is provided on each p-type semiconductor region exposed on the upper face of the semiconductor substrate. The metal electrode portion is in Schottky contact with an n-type semiconductor region exposed on the upper face of the semiconductor substrate, and is in ohmic contact with the semiconductor electrode portion.Type: ApplicationFiled: December 24, 2008Publication date: June 25, 2009Inventors: Hirokazu Fujiwara, Masaki Konishi, Eiichi Okuno
-
Publication number: 20090155998Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.Type: ApplicationFiled: December 24, 2008Publication date: June 18, 2009Inventors: Steven W. Johnston, Kerry Spurgin, Brennan L. Peterson
-
Publication number: 20090148990Abstract: A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide gap regions exposing an upper surface of the substrate, and spacer patterns in the narrow gap regions contacting each other to fill the narrow gap regions, forming an insulating interlayer to cover the spacer patterns and the line patterns, forming at least one opening through the insulating interlayer, the opening including at least one contact hole selectively exposing the upper surface of the substrate in the wide gap region, the contact hole being formed by using the spacer patterns in the narrow gap region as an etching mask, and forming a conductive pattern to fill the opening.Type: ApplicationFiled: November 26, 2008Publication date: June 11, 2009Inventor: Sun-Young Kim
-
Publication number: 20090146254Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.Type: ApplicationFiled: May 6, 2008Publication date: June 11, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Toshiyuki HIROTA
-
Publication number: 20090146129Abstract: A method of manufacturing a semiconductor memory cell including phase change material. A multi-bit memory cell may implement phase change material. Various kinds of information can be stored in one memory cell. A chip size may be minimized without sacrificing capacity and/or memory performance, as compared with a one-bit memory cell.Type: ApplicationFiled: December 9, 2008Publication date: June 11, 2009Inventor: Kwang-Jeon Kim
-
Publication number: 20090146261Abstract: A semiconductor device having a VIA hole without disconnection caused by step is achieved. A semiconductor device and its manufacturing method, the semiconductor device comprising: a semi-insulating substrate 11 in which an electrode (12) is formed on a surface (11a) of one side and in which an aperture (11c) passed through from the surface 11a of one side to a surface (11b) of another side is formed; and a conductive layer (17) formed in an inner surface of the aperture (11c), and electrically connected with the electrode (12); wherein the aperture (11c) has a tapered region (11d) where an inside diameter of a part located in the surface (11b) of another side is larger than an inside diameter of a part located in the surface (11a) of one side.Type: ApplicationFiled: November 28, 2007Publication date: June 11, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ken Onodera, Kazutaka Takagi
-
Publication number: 20090142924Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.Type: ApplicationFiled: December 22, 2008Publication date: June 4, 2009Applicant: International Business Machines CorporationInventors: Chao-Kun Hu, Robert Rosenberg, Judith Marie Rubino, Carlos Juan Sambucetti, Anthony Kendall Stamper
-
Publication number: 20090142915Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer on the substrate, and a gate on the dielectric layer. The gate has first and second ends containing a first material, a middle region between the first and second ends containing a second material. The first material has a different work function than the second material.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Inventor: Weize Xiong
-
Patent number: 7541275Abstract: The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (100), among other elements, includes a surface conductive lead (160) located in an opening formed within a protective overcoat (110), and a barrier layer (140) located between the protective overcoat (110) and the surface conductive lead (160), a portion of the barrier layer (140) forming a skirt (145) that extends outside a footprint of the surface conductive lead (160).Type: GrantFiled: April 21, 2004Date of Patent: June 2, 2009Assignee: Texas Instruments IncorporatedInventors: Betty Shu Mercer, Erika Leigh Shoemaker, Byron Lovell Williams, Laurinda W. Ng, Alec J. Morton, C. Matthew Thompson
-
Publication number: 20090134497Abstract: A structure and method of forming landing pads for through substrate vias in forming stacked semiconductor components are described. In various embodiments, the current invention describes landing pad structures that includes multiple levels of conductive plates connected by vias such that the electrical connection between a through substrate etch and landing pad is independent of the location of the bottom of the through substrate trench.Type: ApplicationFiled: November 26, 2007Publication date: May 28, 2009Inventors: Hans-Joachim Barth, Jens Pohl
-
Publication number: 20090134522Abstract: A method of manufacturing a non-volatile memory bitcell comprises the steps of depositing a first layer of conductive material on a substrate and patterning and etching the first layer of conductive material to form three non-linearly disposed electrodes. The method also comprises the steps of depositing a first layer of sacrificial material on the electrodes and the substrate and providing an elongate cantilever structure on the first layer of sacrificial material such that the cantilever structure and at least a portion of each electrode overlap each other. The method also includes the steps of depositing a second layer of sacrificial material on the cantilever structure and the first layer of sacrificial material and providing a capping layer on the second layer of sacrificial material and providing holes in the capping layer such that at least a portion of the second layer of sacrificial material is exposed.Type: ApplicationFiled: November 22, 2006Publication date: May 28, 2009Applicant: CAVENDISH KINETICS LTD.Inventors: Charles Gordon Smith, Robert Kazinczi, Robertus P. Van Kampen
-
Publication number: 20090127594Abstract: MOS transistors and methods for fabricating MOS transistors are provided. One exemplary method comprises providing a silicon substrate having an impurity-doped region disposed at a surface of the silicon substrate. A first layer is sputter-deposited onto the impurity-doped region using a first sputtering target comprising nickel and a first concentration of platinum. A second layer is sputter-deposited onto the first layer using a second sputtering target comprising nickel and a second concentration of platinum, wherein the second concentration of platinum is less than the first.Type: ApplicationFiled: November 19, 2007Publication date: May 21, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Valli ARUNACHALAM, Paul R. BESSER
-
Publication number: 20090130839Abstract: A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask.Type: ApplicationFiled: January 12, 2009Publication date: May 21, 2009Applicant: CHIPMOS TECHNOLOGIES (BERMUDA) LTD.Inventor: Xuan-Feng Lu
-
Publication number: 20090130840Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.Type: ApplicationFiled: November 16, 2007Publication date: May 21, 2009Inventors: Chung Yu Wang, Chien-Hsiun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
-
Publication number: 20090124078Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.Type: ApplicationFiled: December 30, 2008Publication date: May 14, 2009Applicant: SANYO Electric Co., Ltd.Inventors: Kojiro KAMEYAMA, Akira SUZUKI, Yoshio OKAYAMA, Mitsuo UMEMOTO
-
Publication number: 20090115074Abstract: In a method of processing a contact pad, a passivation layer stack including at least one passivation layer is formed on at least an upper surface of a contact pad region. A first portion of the passivation layer stack is removed from above the contact pad region, wherein a second portion of the passivation layer remains on the contact pad region and covers the contact pad region. An adhesion layer is formed on the passivation layer stack. The adhesion layer is patterned, wherein the adhesion layer is removed from above the contact pad region. Furthermore, the second portion of the passivation layer stack is removed.Type: ApplicationFiled: November 7, 2007Publication date: May 7, 2009Inventors: Markus Hammer, Guenther Ruhl, Andreas Strasser, Michael Melzl, Reinhard Goellner, Doerthe Groteloh
-
Publication number: 20090117730Abstract: Manufacture of semiconductor products such as LCD driver requires a bump plating step for forming a gold bump electrode having a size of from about 15 to 20 ?m. This bump plating step is performed by electroplating with a predetermined plating solution, but projections intermittently appear on the bump electrode during a mass production process. In the invention, abnormal growth of projections over the gold bump electrode is prevented by adding, prior to the gold bump plating step, a step of circulating and stirring a plating solution while erecting a plating cup and efficiently dissolving/discharging a precipitate. This step is performed for each wafer to be treated.Type: ApplicationFiled: October 23, 2008Publication date: May 7, 2009Inventors: Tota MAITANI, Taku Kanaoka
-
Publication number: 20090108400Abstract: An antifuse structure includes a sense pad contact region that is separate from an anode contact region and a cathode contact region. By including the sense pad contact region that is separate from the anode contact region and the cathode contact region, a programming current flow when programming the antifuse structure may travel a different pathway than a sense current flow when sensing the antifuse structure. In particular a sense current flow may avoid a depletion region created within the cathode contact region when programming the antifuse structure.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alberto Cestero, Byeongju Park, John Safran
-
Publication number: 20090098730Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a lower wire, an interlayer insulating film formed on the lower wire and having a via hole exposing the upper surface of the lower wire, a diffusion barrier formed on the inner wall of the via hole, and an upper wire filling the via hole and directly contacting the lower wire, in which a dopant region containing a component of the diffusion barrier is formed in the lower wire in the extension direction of the via hole.Type: ApplicationFiled: December 16, 2008Publication date: April 16, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-hwan Oh, Dong-cho Maeng, Soon-ho Kim
-
Publication number: 20090091233Abstract: Disclosed is a protecting device for electronic circuit and the manufacturing method thereof. The device is a multi-layered structure which includes a dielectric layer and several electrode layers overlapping in the inner circumference of the substrate. After making up a whole structure, a transverse gap with an appropriate depth is formed by cutting process causing two superposed electrode layers to split into two parts facing to each other with respect to the transverse gap and also split into upper and lower parts with respect to the dielectric layer. With this structure, the gap can serve as a protecting element for electrostatic discharge (ESD) or other elements by filling different materials and with the aid of the dielectric layer of appropriate thickness thereby the whole structure can be used to perform surge protection for various electronic circuits.Type: ApplicationFiled: October 3, 2007Publication date: April 9, 2009Inventor: Liu Te-Pang
-
Publication number: 20090072398Abstract: An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material.Type: ApplicationFiled: September 14, 2007Publication date: March 19, 2009Applicant: Qimonda AGInventors: Roland Irsigler, Harry Hedler, Stephan Dobritz
-
Publication number: 20090068829Abstract: A method of manufacturing a semiconductor device comprising forming a conductive layer on a semiconductor substrate; forming a metal layer on the conductive layer; performing a first etching process for patterning the metal layer on a first area to form first metal layer patterns at relatively wide intervals until the conductive layer of the first area is exposed; performing a second etching process for forming an etching-obstructing layer on the first area and patterning the metal layer on a second area to form second metal layer patterns at relatively narrow intervals until the conductive layer of the second area is exposed; removing the etching-obstructing layer; and removing an exposed area of the conductive layer to form a conductive pattern.Type: ApplicationFiled: December 26, 2007Publication date: March 12, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: In No Lee
-
Patent number: 7494941Abstract: At a time of a substrate loading step or/and at a time of a substrate unloading step, particles are effectively eliminated from a reaction chamber. Provided are a step of loading at least one wafer 200 into a reaction chamber 201, a step of introducing reaction gas into the reaction chamber 201, and exhausting an inside of the reaction chamber 201, thereby processing the wafer 200, and a step of unloading the processed wafer 200 from the reaction chamber 201. In the step of loading the wafer 200 or/and in the step of unloading the wafer 200, the inside of the reaction chamber 201 is exhausted at a larger exhaust flow rate than an exhaust flow rate in the step of processing the wafer 200.Type: GrantFiled: November 19, 2004Date of Patent: February 24, 2009Assignee: Hitachi Kokusai Electric Inc.Inventors: Osamu Kasahara, Kiyohiko Maeda, Akihiko Yoneda
-
Publication number: 20090020790Abstract: A method of directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first polysilicon sub-layer on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second polysilicon sub-layer on the first sub-layer. The first and second sub-layers constitute the polysilicon film, and the first bias voltage differs from the second bias voltage.Type: ApplicationFiled: May 6, 2008Publication date: January 22, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Yuan Tseng, I Hsuan Peng, Yung-Hui Yeh, Jung-Jie Huang, Cheng-Ju Tsai
-
Publication number: 20090017624Abstract: An electroless plating method and the apparatus for performing the same are provided. The method includes providing a plating solution; contacting a front surface of the wafer with the plating solution; and incurring a plating reaction substantially simultaneously on an entirety of the front surface of the wafer. The step of incurring a plating reaction substantially simultaneously includes lift-dispense electroless plating and face-down immersion.Type: ApplicationFiled: July 9, 2007Publication date: January 15, 2009Inventors: Chih-Hung Liao, Hung-Wen Su, Chun-Chieh Lin
-
Patent number: 7473634Abstract: A method of copper metallization includes providing a patterned substrate containing a via and a trench, and performing an integrated process on the patterned substrate. The integrated process includes depositing a first metal-containing layer over the patterned substrate, removing by sputter etching the first metal-containing layer from the bottom of the via and at least partially removing the first metal-containing layer from the bottom of the trench, depositing a conformal Ru layer onto the sputter etched first metal-containing layer, depositing a Cu alloying metal layer onto the conformal Ru layer, and plating Cu over the patterned substrate. According to one embodiment, the method can further include depositing a second metal-containing layer onto the sputter etched first metal-containing layer prior to depositing the conformal Ru layer. According to another embodiment, a Cu alloying metal may be deposited onto the plated Cu and the plated Cu annealed.Type: GrantFiled: September 28, 2006Date of Patent: January 6, 2009Assignee: Tokyo Electron LimitedInventor: Kenji Suzuki
-
Publication number: 20090001588Abstract: Methods and apparatus relating to a single silicon wafer having metal and alloy silicides are described. In one embodiment, two different silicides may be provided on the same wafer. Other embodiments are also disclosed.Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Inventor: Pushkar Ranade
-
Publication number: 20080318417Abstract: A method of depositing a ruthenium(Ru) thin film on a substrate in a reaction chamber, includes: (i) supplying a gas of a ruthenium precursor into the reaction chamber so that the gas of the ruthenium precursor is adsorbed onto the substrate, wherein the ruthenium precursor a ruthenium complex contains a non-cyclic dienyl; (ii) supplying an excited reducing gas into the reaction chamber to activate the ruthenium precursor adsorbed onto the substrate; and (iii) repeating steps (i) and (ii), thereby forming a ruthenium thin film on the substrate.Type: ApplicationFiled: September 5, 2008Publication date: December 25, 2008Applicant: ASM JAPAN K.K.Inventors: Hiroshi Shinriki, Hiroaki Inoue
-
Publication number: 20080315420Abstract: A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.Type: ApplicationFiled: June 25, 2007Publication date: December 25, 2008Applicant: Macronix International Co., Ltd.Inventors: Yung-Tai Hung, Jen-Chuan Pan, Chin-Ta Su, Ta-Hung Yang
-
Patent number: 7465676Abstract: A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.Type: GrantFiled: April 24, 2006Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang Wen Tsai, I-I Chen, Zhen-Cheng Wu, Chih-Lung Lin, Tien-I Bao, Shwang-Ming Jeng, Chen-Hua Yu
-
Publication number: 20080299770Abstract: A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.Type: ApplicationFiled: May 31, 2007Publication date: December 4, 2008Inventors: Kyle Kirby, Swarnal Borthakur
-
Publication number: 20080280440Abstract: Disclosed is a method of forming a PN diode and a method of manufacturing a phase change memory device using the same. Formation of a PN diode includes forming a first conductivity type region in a surface of a semiconductor substrate. A polysilicon layer doped with second conductivity type impurities is then deposited on the semiconductor substrate formed with the first conductivity type region. Forming a plurality of second conductivity type regions by etching the polysilicon layer doped with the second conductivity type impurities completes the PN diode. Since the P-regions of a PN diode are formed through the deposition and etching of a polysilicon layer doped with second conductivity type impurities rather than an SEG process, a uniformity of resistance in the PN diode can be obtained.Type: ApplicationFiled: November 12, 2007Publication date: November 13, 2008Inventor: Heon Yong CHANG
-
Publication number: 20080268640Abstract: A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.Type: ApplicationFiled: July 20, 2007Publication date: October 30, 2008Inventors: Yu-Chung Fang, Hong-Wen Lee, Kuo-Chung Chen, Jen-Jui Huang, Jing-Kae Liou
-
Patent number: 7442637Abstract: A method for processing IC designs for different metal BEOL processes is provided for enabling fabricating using a metal fabrication process an IC originally having a backend design for a different metal fabrication process. The method first determines layer constructions of an original design of an IC for a first metal backend process, and, based on the layer constructions of the original design of the IC, constructs primitive layer constructions of a target design of the IC for a second metal backend process. The method then tunes an effective dielectric constant of a dielectric layer of the target design to match an associated capacitance of the target backend design with a corresponding capacitance of the original backend design. The method can be used to convert a backend design of an IC from an old metal process (such as Al process) to a new metal process (such as Cu process), without redesigning the IC for the new metal BEOL fabrication process.Type: GrantFiled: August 15, 2005Date of Patent: October 28, 2008Assignee: Chartered Semiconductor Manufacturing, LtdInventors: Jiannong Su, Simon Shi-ning Yang, Jian Zhang
-
Publication number: 20080248624Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.Type: ApplicationFiled: June 10, 2008Publication date: October 9, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David V. Horak, Chung H. Lam, Hon-Sum P. Wong
-
Publication number: 20080246147Abstract: A novel design and method of fabricating a semiconductor device. In a preferred embodiment, the present invention is a flip chip package including a BT substrate. On the side of the substrate facing the die, thin traces are formed of an enhanced conductive material. Conductive bumps such as eutectic solder balls are then mounted on the traces, and the die mounted to the bumps. The die then packaged and mounted to a printed circuit board using, for example, a ball grid array.Type: ApplicationFiled: April 9, 2007Publication date: October 9, 2008Inventors: Chao-Yuan Su, Chia Hsiung Hsu, Steven Hsu
-
Publication number: 20080247226Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.Type: ApplicationFiled: April 5, 2007Publication date: October 9, 2008Inventors: Jun Liu, Michael P. Violette
-
Publication number: 20080246042Abstract: A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer.Type: ApplicationFiled: September 20, 2007Publication date: October 9, 2008Applicant: AU OPTRONICS CORP.Inventor: Yu-Hsin Ting
-
Publication number: 20080233745Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.Type: ApplicationFiled: April 23, 2007Publication date: September 25, 2008Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
-
Publication number: 20080230905Abstract: In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer.Type: ApplicationFiled: March 19, 2007Publication date: September 25, 2008Inventors: Karsten Guth, Holger Torwesten
-
Publication number: 20080227278Abstract: A method of manufacturing a semiconductor device including an NMOS transistor and a PMOS transistor is provided. The method includes: forming a silicon layer over a substrate through a gate insulating film; forming a first gate electrode and a second gate electrode by patterning the silicon layer, the first gate electrode being a gate electrode of the NMOS transistor, and the second gate electrode being a gate electrode of the PMOS transistor; selectively forming a silicon oxide film on the first gate electrode which is formed of silicon; after the selectively forming the silicon oxide film, forming a first metallic layer formed of a metal capable of forming a silicide over the first and second gate electrodes; and performing a first heat treatment such that a first silicide layer of a silicide of the first metallic layer is formed.Type: ApplicationFiled: March 12, 2008Publication date: September 18, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Takashi HASE
-
Publication number: 20080206986Abstract: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.Type: ApplicationFiled: October 12, 2007Publication date: August 28, 2008Inventors: Axel Preusse, Berit Freudenberg, Michael Friedemann
-
Publication number: 20080206895Abstract: A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD.Type: ApplicationFiled: April 24, 2008Publication date: August 28, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki ASAO, Hiroaki YODA
-
Publication number: 20080203387Abstract: Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor may include a gate; a channel layer; a source and a drain, the source and the drain being formed of metal; and a metal oxide layer, the metal oxide layer being formed between the channel layer and the source and the drain. The metal oxide layer may have a gradually changing metal content between the channel layer and the source and the drain.Type: ApplicationFiled: January 4, 2008Publication date: August 28, 2008Inventors: Dong-hun Kang, Stefanovich Genrikh, I-hun Song, Young-soo Park, Chang-jung Kim
-
Publication number: 20080205132Abstract: It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer.Type: ApplicationFiled: February 20, 2008Publication date: August 28, 2008Inventor: Yoshiharu Hirakata
-
Publication number: 20080197467Abstract: A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially covering the pad to define a first opening portion having a first lateral size. The conductive structure electrically connects to the pad via the first opening portion. The conductive structure comprises a support layer defining a second opening portion. A conductor is formed in the second opening portion to serve as a bump having a planar top surface.Type: ApplicationFiled: September 13, 2007Publication date: August 21, 2008Inventors: J.B. Chyi, Cheng Tang Huang
-
Patent number: 7413971Abstract: An arrangement and process for producing a circuit arrangement is disclosed. The process includes having a layer arrangement, in which two electrically conductive interconnects running substantially parallel to one another are formed on a substrate. At least one auxiliary structure is formed on the substrate and between the two interconnects, running in a first direction, which first direction includes an angle of between 45 degrees and 90 degrees with a connecting axis of the interconnects, running orthogonally with respect to the two interconnects, the at least one auxiliary structure being produced from a material which allows the at least one auxiliary structure to be selectively removed from a dielectric layer. The dielectric layer is formed between the two interconnects, in such a manner that the at least one auxiliary structure is at least partially covered by the dielectric layer.Type: GrantFiled: October 23, 2002Date of Patent: August 19, 2008Inventors: Werner Steinhögl, Franz Kreupl, Wolfgang Hönlein
-
Publication number: 20080179689Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tan-Chen Lee, Chung-Te Lin, Kuang-Hsin Chen, Chi-Hsi Wu, Di-Houng Lee, Cheng-Hung Chang
-
Publication number: 20080178921Abstract: An MOCVD process provides aligned p- and n- type nanowire arrays which are then filled with p- and n-type thermoelectric films to form the respective p-leg and n-leg of a thermoelectric device. The thermoelectric nanowire synthesis process is integrated with a photolithographic microfabrication process. The locations of the p- and n-type nanowire micro arrays are defined by photolithography. Metal contact pads at the bottom and top of these nanowire arrays which link the p- and n-type nanowires in series are defined and aligned by photolithography.Type: ApplicationFiled: August 22, 2007Publication date: July 31, 2008Inventor: Qi Laura Ye
-
Publication number: 20080173979Abstract: A method for fabricating a semiconductor device including preparing a substrate provided with a first storage node contact, forming a second storage node contact over the first storage node contact, the second storage node contact leaning to one side, and forming a storage node of a capacitor over the second storage node contact.Type: ApplicationFiled: November 15, 2007Publication date: July 24, 2008Inventor: Buem-Suck Kim