Abstract: A method is provided. The method includes removing an extracted die including an original ball bond from a previous packaged integrated circuit, bonding the extracted die to an interposer to create a remapped extracted die, 3D printing one or more first bond connections between one or more original bond pads of the extracted die and one or more first bond pads of the interposer, securing the remapped extracted die to a package base, and 3D printing one or more second bond connections between one or more second bond pads of the interposer and one or more package leads or downbonds of the package base. The one or more first and second bond connections conform to the shapes and surfaces of the extracted die, the interposer, and the package base.

Abstract: An optoelectronic semiconductor component includes an optoelectronic semiconductor chip with a first surface and a second surface. The component also includes a protective chip which has a protective diode, a first surface and a second surface. The semiconductor chip and the protective chip are embedded in a molded body. A first electrical contact and a second electrical contact are arranged on the first surface of the semiconductor chip. A third electrical contact and a fourth electrical contact are arranged on the first surface of the protective chip. The first electrical contact is electrically connected to the third electrical contact. In addition, the second electrical contact is electrically connected to the fourth electrical contact.

Abstract: A method for manufacturing a light-emitting element, including steps of: providing a wafer-level element including a wafer and a light-emitting stack on the wafer, wherein the wafer including an upper surface and a bottom surface, and light-emitting stack is formed on the upper surface of the wafer; forming a light-emitting stack on the upper surface of the wafer; cutting the wafer from one of the bottom surface or the top surface of the wafer by a water-jet laser having a first beam size; cutting the wafer from the other one of the bottom surface or the upper surface of the wafer by the water-jet laser having a second beam size; and dividing the wafer-level element wafer and the light-emitting stack into a plurality of light-emitting dies.

Abstract: The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.

Abstract: According to an embodiment, a device includes a substrate, a transducer die disposed over the substrate, a cover disposed over the transducer die, and a support structure connecting the cover to the substrate. The support structure includes a port configured to allow transfer of fluidic signals between an ambient environment and the transducer die.

Abstract: A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each including a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips.

Abstract: A display device includes a first substrate that is non-rectangular and includes a display area having a plurality of pixels and a non-display area located around the display area, a second substrate that faces the first substrate and overlaps part of the first substrate, an integrated circuit that provides a driving signal to the pixels, and a first pad to which a flexible printed circuit board that delivers an external signal is coupled and which is electrically connected to the integrated circuit. The non-display area of the first substrate includes a first area that extends in a first direction and is exposed from the second substrate and a second area that extends in a second direction different from the first direction and is exposed from the second substrate. The integrated circuit is located in the first area. The first pad is located in the second area.

Abstract: Provided is a composition for use in fabricating a carbon molecular sieve membrane, including a fluorine-containing polymer matrix and polysilsesquioxane. The composition shows high selectivity to the gas to be separated and high separation quality by controlling the mixing ratio of the fluorine-containing polymer matrix with polysilsesquioxane as well as the type of fluorine-containing polymer matrix and polysilsesquioxane. Ancillary selective pore formation is enhanced by a so-called “autogenous fluorinated gas induced siloxane etching” (A-FISE) mechanism of fluorine-containing polymer/polysilsesquioxane blend precursors during carbonization. Therefore, it is possible to effectively separate gases having a small difference in particle size, which, otherwise, are difficult to be separated with the conventional polymer membranes.

Abstract: In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.

Abstract: A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package.

Abstract: A semiconductor module is disclosed. The semiconductor module may include a housing having a sidewall portion, a housing support plate coupled to a bottom surface of the sidewall portion such that the housing support plate and the sidewall portion define an interior space of the housing of the semiconductor module, and a semiconductor device disposed within the interior space and fixedly coupled to the housing. The semiconductor module may further include a cover member fixedly attached to a top surface of the sidewall portion such that the cover member, the housing and the housing support plate form a protective enclosure for the semiconductor device.

Abstract: Encapsulated semiconductor packages and methods of production thereof. As a non-limiting example, a semiconductor package may be produced by partially dicing a wafer, molding the partially diced wafer, and completely dicing the molded and partially diced wafer.

Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.

Abstract: Disclosed herein are a thin film common mode filter and a method of manufacturing the same. The thin film common mode filter according to the exemplary embodiment of the present invention includes a magnetic substrate made of a magnetic ceramic material; and coil patterns formed on the magnetic substrate, wherein external electrodes connected with the coil patterns are sequentially stacked and insulating layers formed on and beneath the coil pattern are made of a composite of ferrite powder and thermosetting resin.

Abstract: A method for forming semiconductor device package comprises providing a substrate with via contact pads and via through holes through said substrate, terminal pads on a bottom surface of said substrate and an exposed type through hole through said substrate. A die is provided with bonding pads thereon and an exposed type pad on a bottom surface of said die. A reflective layer is formed on an upper surface of the substrate. The die is adhered on the substrate. A dry film is formed on a top of the die as a slanting structure. A re-distribution layer conductive trace is formed by sputtering and E-plating on an upper surface of the slanting structure.

Abstract: A quartz vibrator that includes a substrate, a quartz vibrating element, and a dome-shaped cap. The quartz vibrating element is mounted on the substrate. The cap is bonded to the substrate. The cap defines and forms a sealed space that seals the quartz vibrating element along with the substrate. The cap has a side wall portion, a ceiling portion, and a connecting portion. The side wall portion encloses the quartz vibrating element. The ceiling portion is positioned above the quartz vibrating element. The connecting portion connects the side wall portion and the ceiling portion. The connecting portion is thinner than the side wall portion and the ceiling portion.

Abstract: In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module.

Abstract: A disclosed circuit arrangement includes a flexible substrate. A layer of pressure sensitive adhesive (PSA) is directly adhered to a first major surface of the substrate. One or more metal foil pads and electrically conductive wire are attached directly on a surface of the PSA layer. The wire has a round cross-section and one or more portions directly connected to the one or more metal foil pads with one or more weld joints, respectively. An electronic device is attached directly on the surface of the layer of PSA and is electrically connected to the one or more portions of the round wire by one or more bond wires, respectively.

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

Abstract: A method for mounting a rigid electrical connector, including selecting an electrical connector that is compatible with a predetermined portable electronic device; forming an aperture through an interface member, wherein the aperture is larger than the electrical connector; selecting an elastomeric potting material that is compatible with both the electrical connector and the interface member; locating the electrical connector in the aperture with a space between the electrical connector and the interface member; introducing the elastomeric potting material in an uncured state into the space between the electrical connector and the interface member; and while maintaining the space between the electrical connector and the interface member, curing the elastomeric potting material in the space therebetween.

Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.

Abstract: A solution for packaging an optoelectronic device using an ultraviolet transparent polymer is provided. The ultraviolet transparent polymer material can be placed adjacent to the optoelectronic device and/or a device package on which the optoelectronic device is mounted. Subsequently, the ultraviolet transparent polymer material can be processed to cause the ultraviolet transparent polymer material to adhere to the optoelectronic device and/or the device package. The ultraviolet transparent polymer can be adhered in a manner that protects the optoelectronic device from the ambient environment.

Abstract: Disclosed embodiments include a manufacturing method for an LED assembly. Providing a first carrier, wherein several LED chips are formed on the first carrier, and providing a second carrier. Attaching the second carrier to the LED chips and detaching the first carrier from the LED chips but leaving the LED chips on the second carrier.

Abstract: The method of fabricating a semiconductor package including preparing a semiconductor wafer having a first side and a second side, the second side facing the first side, and the semiconductor wafer including a through via exposed through the first side, forming trenches at cutting areas between chip areas and at edge areas of the semiconductor wafer on the first side, stacking a semiconductor chip on the through via, forming an under fill resin layer to fill a gap between the semiconductor chip and the semiconductor wafer and to cover a side of the semiconductor chip, and forming a molding layer to cover at least a portion of the under fill resin layer and to fill at least a portion of the respective trenches may be provided.

Abstract: The semiconductor package includes: a substrate having a window and first and second bond fingers arranged over a first surface along a periphery of the window; a first semiconductor chip disposed within the window and having a plurality of first bonding pads arranged over edges of an upper surface; a plurality of first connection members electrically coupling the first bonding pads with the first bonding fingers; a second semiconductor chip disposed over the first semiconductor chip and the first surface of the substrate and a plurality of second bonding pads in the edges of the lower surface; a plurality of second connection members electrically coupling the second bonding pads with the second bonding fingers of the substrate adjacent to the second bonding pads; and an encapsulation member formed over the first surface of the substrate to cover side surfaces of the second semiconductor chip.

Abstract: The present invention provides a package method of a substrate and a package structure. The method comprises: step 1, providing the substrate (1) and a package plate (3), and the package plate (3) comprises a spreading surface (31); step 2, forming at least one groove (311); step 3, spreading seal glue (50) to form the continuous frame (5), and a recess (51) is formed in the frame (5) corresponding to the groove (311); step 4, positioning underfill (70) inside an area surrounded by the frame (5); step 5, oppositely fitting the substrate (1) and the package plate (3), and an air outlet (20) is formed at a position of the recess (51) of the frame (5) between the substrate (1) and the package plate (3); step 6, extracting air between the substrate (1) and the package plate (3) through the air outlet (20); step 7, laminating the substrate (1) and the package plate (3); step 8, irradiating and solidifying the seal glue (50) and the underfill (70) with UV light.

Abstract: The electronic device is provided with a wiring board, a piezoelectric element (electronic component) which is mounted on an upper surface (front surface) of the wiring board so as to make its functional surface (major surface) face the upper surface, and a resin part which is adhered to a side surfaces of the piezoelectric element and to the wiring board and seals a facing space between the upper surface of the wiring board and the functional surface of the piezoelectric element. Further, the resin part is recessed in shape relative to the facing space.

Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

Abstract: An electronic component has a mounting board having a mounting surface, a SAW device mounted on the mounting surface, and a sealing part covering the SAW device and filled between the SAW device and the mounting surface. The SAW device has an element substrate, an excitation electrode provided on a major surface of the element substrate and a cover covering the excitation electrode. SAW device is mounted on the mounting surface so as to make top surfaces of the cover face the mounting surface. The sealing part contains a resin and insulating fillers having a coefficient of thermal expansion lower than that of the resin. The content of the fillers differs between an area (for example AR1) including at least a portion of an area between the cover and the mounting surface and other areas (for example AR2 and AR3).

Abstract: An exemplary embodiment described technology relates generally to an organic light emitting diode (OLED) display and a manufacturing method thereof. The organic light emitting diode (OLED) display according to an exemplary embodiment includes: a substrate; an encapsulation member; an organic light emitting element between the substrate and the encapsulation member; a middle sealing member including one side disposed between the substrate and the encapsulation member and another side extended from the one side to be bent and enclosing an edge of the encapsulation member; a first sealant sealing and combining the one side of the middle sealing member and the substrate to each other; a second sealant sealing and combining the other side of the middle sealing member and the encapsulation member to each other; and a getter at the one side of the middle sealing member and the encapsulation member.

Abstract: Described are embodiments to ensure that the equipment utilized to detect antigens is reliable and accurate. Accordingly, one embodiment of the invention includes a calibration assembly having nanoparticles, with known magnetic properties, spaced apart at known y-axis locations along the calibration assembly. In one embodiment, the calibration assembly may be used to calibrate a matched filter of the write and read circuitry. Because the calibration assembly comprises nanoparticles with known magnetic properties the read response of the read circuitry to a particular nanoparticle may be stored in the matched filter as an ideal signal for that nanoparticle. The ideal signal stored in the matched filter may then be utilized for reliably and accurately detecting antigens.

Abstract: A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the molded package, such as on top of a device die mounted on the package substrate or a lead frame. In order to overcome cavity wall angular limitations introduced by conformability issues associated with film-assisted molding, a gel reservoir feature is formed so that gel used to protect components in the cavity does not come in contact with a lid covering the cavity or the junction between the lid and the package attachment region. The gel reservoir is used in conjunction with a formed level setting feature that controls the height of gel in the cavity. Benefits include decreased volume of the cavity, thereby decreasing an amount of gel-fill needed and thus reducing production cost of the package.

Abstract: A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 ?m to 8.00 ?m deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle.

Abstract: An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities.

Abstract: A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill.

Abstract: A light-emitting device production method includes a positioning step of positioning, in a light-emitting element, a sealing member at least containing a silicone resin semi-cured at a room temperature (T0) by primary cross-linking and a fluorescent material, the silicone resin decreasing in viscosity reversibly in a temperature region between the room temperature (T0) and a temperature lower than a secondary cross-linking temperature (T1), and being totally cured non-reversibly in a temperature region equal to or higher than the secondary cross-linking temperature (T1).

Abstract: Method and apparatus for semiconductor device fabrication using a reconstituted wafer is described. In one embodiment, diced semiconductor chips are placed within openings on a frame. A reconstituted wafer is formed by filling a mold compound into the openings. The mold compound is formed around the chips. Finished dies are formed within the reconstituted wafer. The finished dies are separated from the frame.

Abstract: A process for encapsulating a micro-device in a cavity formed between a first and a second substrate is provided, including producing the micro-device in or on the first substrate; attaching and securing the second substrate to the first substrate, thereby forming the cavity in which the micro-device is placed; producing at least one hole through one of the two substrates, leading into the cavity opposite a portion of the other of the two substrates; depositing at least one getter material portion through the hole on said portion of the other of the two substrates; and hermetically sealing the cavity by closing the hole.

Abstract: Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.

Abstract: A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.

Abstract: Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate nearly to an upper surface of the filler layer. In some embodiments of electronic packages, the through contacts separated from the heat sink by a trench cut into the upper surface of the filler layer, the through contacts intersecting one wall of the trench and the heat sink intersecting the other wall of the trench an electronic semiconductor package. A method of forming the package and a lead frame are also disclosed.

Abstract: A method for constructing an electrical circuit that includes at least one semiconductor chip encapsulated with a potting compound is disclosed. The method includes applying a galvanic layer arrangement for forming an electrochemical element on an element of the electrical circuit including the at least one semiconductor chip.

Abstract: A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.

Abstract: A method of manufacture of a semiconductor package system includes: attaching an internal stacking module die to a surface of an internal stacking module substrate having an internal stacking module bonding pad along an edge of an opposite surface thereof; and attaching a support carrier to support the internal stacking module substrate by two edges thereof with the internal stacking module bonding pad exposed.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: Disclosed is a polyimide composition for semiconductor devices, which has a rheological characteristics suited for screen printing and dispense coating, which has an improved wetting property with various coating bases, by which continuous printing of 500 times or more can be attained, with which blisters, cissing and pinholes are not generated after printing and drying or during drying or curing, which can coat a desired area. A method of forming a film in a semiconductor and semiconductors having the film formed by this method as an insulation film, protective film or the like are also disclosed. The composition for semiconductor devices contains a mixed solvent of a first organic solvent (A) and a second organic solvent (B); and a polyimide resin having at least one group selected from the group consisting of alkyl groups and perfluoroalkyl groups in recurring units, and having thixotropic property, the polyimide resin being dissolved in the mixed solvent.

Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.

Abstract: A microelectronic assembly 5 can include first and second microelectronic packages 10a, 10b mounted to respective first and second opposed surfaces 61, 62 of a circuit panel 60. Each microelectronic package 10a, 10b can include a substrate 20 having first and second apertures 26a, 26b extending between first and second surfaces 21, 22 thereof, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface of the substrate and a plurality of contacts 35 exposed at the surface of the respective microelectronic element and aligned with at least one of the apertures, and a plurality of terminals 25a exposed at the second surface in a central region 23 thereof. The apertures 26a, 26b of each substrate 20 can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 of each substrate 20 can be disposed between the first and second axes 29a, 29b of the respective substrate 20.