Abstract: Variable resistance devices and neural network processing systems include a first phase change memory device that has a first material that increases resistance when a set pulse is applied. A second phase change memory device has a second material that decreases resistance when a set pulse is applied.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.

Abstract: Germanium antimony telluride materials are described, e.g., material of the formula GexSbyTezCmNn, wherein x is about 0.1-0.6, y is about 0-0.7, z is about 0.2-0.9, m is about 0.02-0.20, and n is about 0.2-0.20. One specific composition includes from 0 to 50% Sb, from 50 to 80% Te, from 20 to 50% Ge, from 3 to 20% N and from 2 to 15% carbon, wherein all atomic percentages of all components of the film total to 100 atomic %. Another specific composition includes from 10 to 50% Sb, from 50 to 80% Te, from 10 to 50% Ge, from 3 to 20% N and from 3 to 20% carbon, and wherein all atomic percentages of all components of the film total to 100 atomic %. Material of such composition is useful to form phase change films, e.g., as conformally coated on a phase change memory device substrate to fabricate a phase change random access memory cell.

Abstract: A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode.

Abstract: A method for fabricating a variable resistance device includes: providing a first insulating layer having a first electrode; forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer; forming a sacrifice pattern over the first oxide layer; forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen; removing the sacrifice pattern; and forming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer.

Abstract: A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package.

Abstract: A memory element, including: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing an oxide, and the resistance change layer being provided on the first electrode side, and an ion source layer in a stacking structure of two or more of a unit ion source layer, the unit ion source layer including a first layer and a second layer, the first layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and an easy-to-move element that is easy to move in the memory layer, and having a density distribution of the easy-to-move element from the first electrode to the second electrode, and the second layer containing a difficult-to-move element that is difficult to move in the memory layer.

Abstract: A method of forming a semiconductor device structure. The method comprises forming a block copolymer assembly comprising at least two different domains over an electrode. At least one metal precursor is selectively coupled to the block copolymer assembly to form a metal-complexed block copolymer assembly comprising at least one metal-complexed domain and at least one non-metal-complexed domain. The metal-complexed block copolymer assembly is annealed in to form at least one metal structure. Other methods of forming a semiconductor device structures are described. Semiconductor device structures are also described.

Abstract: A wafer attaching method of attaching a wafer having a warp to a sheet includes a wafer warp detecting step of detecting a surface shape of the wafer, a wafer positioning step of applying a photocuring liquid resin to the sheet and positioning the wafer so that a predetermined surface of the wafer corresponding to attaching conditions preset in a resin bonding apparatus is opposed to the sheet and the liquid resin according to the preset attaching conditions and the surface shape detected above, and a wafer attaching step of pressing the wafer against the liquid resin to thereby spread the liquid resin over the entire area where the wafer and the sheet are superimposed, next removing the pressure applied to the wafer, and next applying light to the liquid resin to cure the liquid resin, thereby attaching the predetermined surface of the wafer to the sheet.

Abstract: A MEMS manufacturing method and device in which a spacer layer is provided over a side wall of at least one opening in a structural layer which will define the movable MEMS element. The opening extends below the structural layer. The spacer layer forms a side wall portion over the side wall of the at least one opening and also extends below the level of the structural layer to form a contact area.

Abstract: A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments.

Abstract: Integrated devices and methods for packaging the same can include an external housing, an internal housing positioned within the external housing, and an external cavity formed between the external housing and the internal housing. An integrated device die can be positioned within the external cavity in fluid communication with an internal cavity formed by the internal lid. An air way can extend through the external cavity to the internal cavity, and can further extend from the internal cavity to the external cavity. The air way can provide fluid communication between the package exterior and the integrated device die, while reducing contamination of the integrated device die.

Abstract: According to one embodiment, a memory cell includes a resistance change layer, an upper electrode layer, a lower electrode layer, a diode layer, a first oxide film, and a second oxide film. The upper electrode layer is arranged above the resistance change layer. The lower electrode layer is arranged below the resistance change layer. The diode layer is arranged above the upper electrode layer or below the lower electrode layer. The first oxide film exists on a side wall of at least one electrode layer of the upper electrode layer or the lower electrode layer. The second oxide film exists on a side wall of the diode layer. The film thickness of the first oxide film is thicker than a film thickness of the second oxide film.

Abstract: The present invention discloses a micrometer-scale grid structure based on single crystal silicon consists of periphery frame 1 and grid zone 2. The periphery frame 1 is rectangle, and grid zone 2 has a plurality of mesh-holes 3 distributing in the plane of grid zone 2. The present invention also provides a method for manufacturing a micrometer-scale grid structure based on single crystal silicon. According to the present invention thereof, the contradiction between demand of broad deformation space for sensor and actuator and the limit of the thickness of sacrifice layer is solved. Furthermore, the special requirement of double-side transparence for some optical sensor is met.

Abstract: A semiconductor pressure sensor includes a first substrate having a concave portion and an alignment mark at a main surface thereof, and a second substrate formed on the main surface of the first substrate and having a diaphragm provided to cover a space inside the concave portion of the first substrate and a gauge resistor provided on the diaphragm. The alignment mark is provided to be exposed from the second substrate. Accordingly, it is possible to obtain a semiconductor pressure sensor and a method of manufacturing the same with reduced production costs and with improved pressure measuring accuracy.

Abstract: A fully embedded micromechanical device and a system on chip is manufactured on an SOI-substrate. The micromechanical device comprises a moveable component having a laterally extending upper and lower surface and vertical side surfaces. The upper surface is adjacent to an upper gap which laterally extends over at least a part of the upper surface and results from the removal of a shallow trench insulation material. The lower surface is adjacent to a lower gap which laterally extends over at least a part of the lower surface and results from the removal of the buried silicon oxide layer. The side surfaces of the movable component are adjacent to side gaps which surround at least a part of the vertical side surfaces of the moveable component and result from the removal of a deep trench insulation material.

Abstract: Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective material extends across an interface of the carbon-containing material and the oxygen-sensitive material, and does not extend to a top region of the carbon-containing material. Second protective material is formed across the top of the carbon-containing material, with the second protective material having a common composition to the first protective material. The second protective material is etched to expose an upper surface of the carbon-containing material. Some embodiments include semiconductor constructions, memory arrays and methods of forming memory arrays.

Abstract: A resistive memory device includes a plurality of resistive units, each resistive unit including: a lower electrode formed over a substrate; a resistive layer formed over the lower electrode; and an upper electrode formed over the resistive layer, wherein edge parts of the lower and upper electrodes, which come in contact with the resistive layer, is formed with a rounding shape.

Abstract: Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.

Abstract: Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.

Abstract: A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments. The switching performance of a resistive memory device based on such an interfacial oxide layer is equivalent or superior to the performance of a conventional resistive memory element.

Abstract: Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. A sealing material is formed on the exposed portion of the at least one of the active storage element material and the active select device material and the trench is deepened such that a portion of the other of the at least one of the active storage element material and the active select device material is exposed on the sidewalls of the trench.

Abstract: A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a dielectric layer on the bottom electrode, and forming a sacrificial layer on the dielectric layer. The method further includes selectively etching portions of the sacrificial layer and the dielectric layer to define a pore extending through the sacrificial layer and the dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.

Abstract: Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.

Abstract: Resistive memory cells having a plurality of heaters and methods of operating and forming the same are described herein. As an example, a resistive memory cell may include a resistance variable material located between a first electrode and a second electrode, a first heater coupled to a first portion of the resistance variable material, a second heater coupled to a second portion of the resistance variable material, a third heater coupled to a third portion of resistance variable material, and a conductive material coupled to the first, second, and third heaters.

Abstract: A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area; a second plug formed in the first oxide layer and the nitride layer of the voltage application area; a conductive line formed in the second oxide layer; a third oxide layer formed on the second oxide layer; a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug; and a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form.

Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction.

Abstract: A method of manufacturing a phase-change memory device comprises forming a contact region on a substrate, forming a lower electrode electrically connected to the contact region, forming a phase-change material layer on the lower electrode using a chalcogenide compound target including carbon and metal, or carbon, nitrogen and metal, and forming an upper electrode on the phase-change material layer.

Abstract: Non-volatile memory elements, memory devices including the same, and methods for operating and manufacturing the same may include a memory layer between a first electrode and a second electrode spaced apart from the first electrode. The memory layer may include a first material layer and a second material layer, and may have a resistance change characteristic due to movement of ionic species between the first material layer and the second material layer. At least the first material layer of the first and second material layers may be doped with a metal.

Abstract: To provide a high-performance semiconductor device using an SOI substrate in which a substrate having low heat resistance is used as a base substrate, to provide a high-performance semiconductor device without performing mechanical polishing, and to provide an electronic device using the semiconductor device, planarity of a semiconductor layer is improved and defects in the semiconductor layer are reduced by laser beam irradiation. Accordingly, a high-performance semiconductor device can be provided without performing mechanical polishing. In addition, a semiconductor device is manufactured using a region having the most excellent characteristics in a region irradiated with the laser beam. Specifically, instead of the semiconductor layer in a region which is irradiated with the edge portion of the laser beam, the semiconductor layer in a region which is irradiated with portions of the laser beam except the edge portion is used as a semiconductor element.

Abstract: A method of forming a semiconductor device structure. The method comprises forming a block copolymer assembly comprising at least two different domains over an electrode. At least one metal precursor is selectively coupled to the block copolymer assembly to form a metal-complexed block copolymer assembly comprising at least one metal-complexed domain and at least one non-metal-complexed domain. The metal-complexed block copolymer assembly is annealed in to form at least one metal structure. Other methods of forming a semiconductor device structures are described. Semiconductor device structures are also described.

Abstract: A semiconductor pressure sensor includes a first substrate having a concave portion and an alignment mark at a main surface thereof, and a second substrate formed on the main surface of the first substrate and having a diaphragm provided to cover a space inside the concave portion of the first substrate and a gauge resistor provided on the diaphragm. The alignment mark is provided to be exposed from the second substrate. Accordingly, it is possible to obtain a semiconductor pressure sensor and a method of manufacturing the same with reduced production costs and with improved pressure measuring accuracy.

Abstract: Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.

Abstract: A method of manufacturing a resistive memory device is provided. A bottom electrode and a cup-shaped electrode connected to the bottom electrode are formed in an insulating layer. A cover layer extends along a first direction is formed and covers a first area surrounded by the cup-shaped electrode and exposes a second area and a third area surrounded by the cup-shaped electrode. A sacrificial layer is formed above the insulating layer. A stacked layer extends along a second direction and covers the second area surrounded by the cup-shaped electrode and a portion of the corresponding cover layer is formed. A conductive spacer material layer is formed on the stacked layer and the sacrificial layer. By using the sacrificial layer as an etch stop layer, the conductive spacer material layer is etched to form a conductive spacer at the sidewall of the stacked layer.

Abstract: A circuit structure with a capacitor or a resistor includes a semiconductor substrate, a first conductive region positioned in the semiconductor substrate, a plurality of second conductive regions and third conductive regions positioned in the first conductive region, a first depletion region positioned between the first conductive region and the third conductive region, a second depletion region positioned between the second conductive region and the third conductive region, and a plurality of separating regions positioned in the first conductive region, configured to separate the second and the third conductive regions. In operation, a first voltage is applied to the separating region to control the capacitance or the resistance of the circuit structure. A second voltage is applied to the first conductive region and a third voltage is applied to the second conductive region to measure the capacitance and the resistance of the circuit structure.

Abstract: In one example, an integrated circuit includes two integrated circuit dies that are face-to-face mounted together. The first integrated circuit die includes passive variable resistance memory and the second integrated circuit die includes memory control logic (e.g., CMOS logic circuit). The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of the passive variable resistance memory on the first integrated circuit die is electrically connected to the memory control logic on the second integrated circuit die through at least one vertical interconnect accesses (vias). For example, the operation (e.g., write/read) of each passive variable resistance memory cell is controlled by the memory control logic. The integrated circuit may also include processor logic on the second integrated circuit die operatively coupled to the memory control logic.

Abstract: A semiconductor component is provided having a substrate and at least one semiconductor layer realized to be polycrystalline on one side of the substrate. The polycrystalline semiconductor layer contains the crystal nuclei.

Abstract: A memory element includes: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, and an ion source layer containing one or more of metallic elements, and the ion source layer being provided on the second electrode side. The ion source layer includes a first ion source layer and a second ion source layer, the first ion source layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and being provided on the resistance change layer side, and the second ion source layer containing the chalcogen element with a content different from a content in the first ion source layer and being provided on the second electrode side.

Abstract: A process for manufacturing a PCM device comprises forming a dielectric, producing a via in the dielectric starting at an area on the surface of the dielectric by forming a via opening in the area and extending the opening into the dielectric toward and then terminating at an electrode comprising a first electrode in the dielectric. We form a spacer layer contiguous with the side walls of the via and fill the via with a PCM. We then remove the surface of the dielectric to leave a PCM cusp at the opening of the via, cap the PCM cusp with a low density capping film; densify the PCM and capping film to obtain a high density capping film that exerts compressive pressure on the high density PCM in a direction toward the first electrode to enhance electrical contact between the PCM and the first electrode.

Abstract: A memory element, including: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing an oxide, and the resistance change layer being provided on the first electrode side, and an ion source layer in a stacking structure of two or more of a unit ion source layer, the unit ion source layer including a first layer and a second layer, the first layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and an easy-to-move element that is easy to move in the memory layer, and having a density distribution of the easy-to-move element from the first electrode to the second electrode, and the second layer containing a difficult-to-move element that is difficult to move in the memory layer.

Abstract: A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings.

Abstract: The present invention is directed to a method for the fabrication of electron field emitter devices, including carbon nanotube (CNT) field emission devices. The method of the present invention involves depositing one or more electrically conductive thin-film layers onto a electrically conductive substrate and performing lithography and etching on these thin film layers to pattern them into the desired shapes. The top-most layer may be of a material type that acts as a catalyst for the growth of single- or multiple-walled carbon nanotubes (CNTs). Subsequently, the substrate is etched to form a high-aspect ratio post or pillar structure onto which the previously patterned thin film layers are positioned. Carbon nanotubes may be grown on the catalyst material layer. The present invention also described methods by which the individual field emission devices may be singulated into individual die from a substrate.

Abstract: This disclosure is directed to a phase change semiconductor device and a manufacturing method thereof, comprising: forming an insulating layer on a substrate and a metal layer on the insulating layer; forming a via hole penetrating from the metal layer to the insulating layer; forming a phase change material layer on the metal layer and the via hole to at least fill up the via hole; and performing a planarization process, wherein after forming the metal layer and before forming the via hole, or after forming the via hole and before forming the phase change material layer, or after forming the phase change material layer and before the planarization process, subjecting the metal layer to an annealing treatment to form a metallic compound layer at an interface between the metal layer and the insulating layer. Adhesion between the phase change material layer and the insulating layer can be improved.

Abstract: The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.

Abstract: According to one embodiment, a memory cell includes a resistance change layer, an upper electrode layer, a lower electrode layer, a diode layer, a first oxide film, and a second oxide film. The upper electrode layer is arranged above the resistance change layer. The lower electrode layer is arranged below the resistance change layer. The diode layer is arranged above the upper electrode layer or below the lower electrode layer. The first oxide film exists on a side wall of at least one electrode layer of the upper electrode layer or the lower electrode layer. The second oxide film exists on a side wall of the diode layer. The film thickness of the first oxide film is thicker than a film thickness of the second oxide film.

Abstract: On example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and a device layer. The device layer comprises a first dielectric material, between the first and second conductive electrodes, that includes an effective device layer, a first barrier layer near a first interface between the first conductive electrode and the device layer, and a second barrier layer near a second interface between the second conductive electrode and the device layer. A second example of the present invention is an integrated circuit that incorporates nanoscale electronic devices of the first example.

Abstract: A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material.

Abstract: A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines.

Abstract: A method of manufacturing a phase-change memory device comprises forming a contact region on a substrate, forming a lower electrode electrically connected to the contact region, forming a phase-change material layer on the lower electrode using a chalcogenide compound target including carbon and metal, or carbon, nitrogen and metal, and forming an upper electrode on the phase-change material layer.

Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.