For Structural Parameters, E.g., Thickness, Line Width, Refractive Index, Temperature, Warp, Bond Strength, Defects, Optical Inspection, Electrical Measurement Of Structural Dimensions, Metallurgic Measurement Of Diffusions (epo) Patents (Class 257/E21.53)
  • Patent number: 11967535
    Abstract: A product includes a semiconductor substrate, with at least first and second thin-film layers disposed on the substrate and patterned to define a matrix of dies, which are separated by scribe lines and contain active areas circumscribed by the scribe lines. A plurality of overlay targets are formed in the first and second thin-film layers within each of the active areas, each overlay target having dimensions no greater than 10 ?m×10 ?m in a plane parallel to the substrate. The plurality of overlay targets include a first linear grating formed in the first thin-film layer and having a first grating vector, and a second linear grating formed in the second thin-film layer, in proximity to the first linear grating, and having a second grating vector parallel to the first grating vector.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 23, 2024
    Assignee: KLA CORPORATION
    Inventors: Amnon Manassen, Vladimir Levinski, Ido Dolev, Yoram Uziel
  • Patent number: 11835854
    Abstract: An imprint device includes a load port for receiving a substrate to be processed, a sensor that acquires information from the substrate about a film on the substrate, and a primer forming unit configured to receive the substrate from the load port. A controller is configured to select primer process conditions corresponding to the film information. The primer forming unit receives primer process conditions from the controller and forms a primer layer on the substrate over the film. The primer layer is formed according to the selected process conditions. An imprinting unit of the imprint device is configured to receive the substrate from the primer forming unit and perform imprint lithography on the substrate.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: December 5, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Kasumi Okabe, Hirokazu Kato, Kei Kobayashi, Daizo Muto
  • Patent number: 11821964
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
  • Patent number: 11788923
    Abstract: A method for detecting a gas tightness of a furnace tube device includes: providing a test wafer; conveying the test wafer into the furnace tube device; depositing a dielectric layer on the test wafer; measuring a thickness and a Goodness of Fit (GOF) of the dielectric layer formed on the test wafer by a thickness measuring machine; and judging the gas tightness of the furnace tube device according to the GOF.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: October 17, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zhipeng Gao
  • Patent number: 11737254
    Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hsin Chiu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-An Lai
  • Patent number: 11724352
    Abstract: A wafer processing method in which a wafer including devices on a front surface side is processed. The method includes a wafer-with-protective-component forming step of forming the wafer with a protective component through sticking the protective component formed of a resin that softens by heat to the front surface side by pressing and heating the protective component, a thickness measurement step of measuring a thickness of the protective component in the wafer with the protective component, and a grinding step of holding the wafer with the protective component by a chuck table and grinding a back surface side of the wafer until a thickness of the wafer becomes an intended finished thickness. In the grinding step, the thickness of the protective component measured in the thickness measurement step is subtracted from a total thickness of the wafer with the protective component to calculate the thickness of the wafer.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: August 15, 2023
    Assignee: DISCO CORPORATION
    Inventors: Toshiyuki Sakai, Heidi Lan
  • Patent number: 11703391
    Abstract: An apparatus for processing substrates includes a continuum radiation source, a source manifold optically coupled to the continuum radiation source and comprising: a plurality of beam guides, each having a first end that optically couples the beam guide to the continuum radiation source; and a second end. The apparatus also includes a detector manifold to detect radiation originating from the source manifold and transmitted through a processing area, and one or more transmission pyrometers configured to analyze the source radiation and the transmitted radiation to determine an inferred temperature proximate the processing area.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 18, 2023
    Assignee: Applied Materials, Inc.
    Inventor: Samuel C. Howells
  • Patent number: 11688717
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hung Wang, Yeong-Jyh Lin, Ching I Li, Tzu-Wei Yu, Chung-Yi Yu
  • Patent number: 11673229
    Abstract: There is provided a processing apparatus that polishes the back surface side of a wafer on which devices are formed on the front surface side. The processing apparatus includes a chuck table that holds the wafer and rotates and a polishing unit that forms scratches on the back surface side of the wafer while polishing the back surface side of the wafer. The processing apparatus includes also a scratch determining unit that determines whether or not the scratches exist on the back surface side of the wafer polished by the polishing unit and an informing unit that informs that a region in which the scratches do not exist is included in the wafer when a region for which it has been determined that the scratches do not exist by the scratch determining unit is included in the wafer.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 13, 2023
    Assignee: DISCO CORPORATION
    Inventor: Toshiyuki Sakai
  • Patent number: 11674220
    Abstract: Methods for forming molybdenum layers on a surface of a substrate and structures and devices formed using the methods are disclosed. Exemplary methods include forming an underlayer prior to forming the molybdenum layer. The underlayer can be used to manipulate stress in the molybdenum layer and/or reduce a nucleation temperature and/or deposition temperature of a step of forming the molybdenum layer.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: June 13, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Paul Ma, Roghayyeh Lotfi, Jaebeom Lee, Eric Christopher Stevens, Amit Mishra
  • Patent number: 11664363
    Abstract: A method for manufacturing a light emitting device including forming a plurality of first light emitting cells and a plurality of second light emitting cells on one surface of a first substrate, providing a second substrate to face the first and second light emitting cells, selectively bonding the first light emitting cells onto the second substrate, and cutting the second substrate to a mounting unit including at least two first light emitting cells.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: May 30, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Chung Hoon Lee
  • Patent number: 11498213
    Abstract: A system includes a robot arm with multiple joints and one or more end effector to carry a substrate. A processing device determines, within joint space of the robot arm, start/end points of the one or more end effector for a complete movement. The processing device builds, in joint space for the multiple joints and the one or more end effector, a graph of reachable positions and sub-paths between the reachable positions that satisfy Cartesian limits. The reachable positions are identified at a granularity that divides the complete movement into multiple sub-movements. The processing device executes a graph optimization algorithm on the graph to determine multiple paths, each a group of the sub-paths, that have one of shortest distances or lowest costs between the start/end points, and selects a path thereof that minimizes move time of the one or more end effector between the start/end points.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: November 15, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Omar Abdul-hadi, Adam Christopher Cranmer, Gregory John Freeman
  • Patent number: 11456253
    Abstract: A semiconductor device includes a main circuit region; and a scribe region surrounding the main circuit region; wherein the main circuit region and the scribe region comprises first and second insulating films and a low-k film formed therebetween; and wherein the low-k film of the scribe region includes a plurality of cavities lining along a border between the main circuit region and the scribe region.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita, Raj K. Bansal
  • Patent number: 11448080
    Abstract: A vane guide assembly for a gas turbine engine, the vane guide assembly including: an airfoil having an end bonded to an opening of a platform by an adhesive; and a pull tab partially located in the adhesive and having a portion extending from a bondline formed by the adhesive.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: September 20, 2022
    Assignee: RAYTHEON TECHNOLOGIES CORPORATION
    Inventor: Xiomara Irizarry-Rosado
  • Patent number: 11371831
    Abstract: The invention relates to a method for determining the thickness and refractive index of a layer (6) on a substrate (26). The layer (6) having a layer boundary surface (30) facing the substrate (26) and a layer top side (28) facing away from the substrate (26).
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 28, 2022
    Assignee: Carl Zeiss Microscopy GmbH
    Inventors: Nils Langholz, Jakob Haarstrich
  • Patent number: 11353479
    Abstract: A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: June 7, 2022
    Assignee: FEI EFA, Inc.
    Inventors: Praveen Vedagarbha, Derryck Reid, Keith Serrels, James S. Vickers
  • Patent number: 11262320
    Abstract: A mercury emissions monitor includes a mercury sensor tape configured to be fed in a reel-to-reel manner between first and second tape reels, wherein the mercury sensor tape includes a thin metallic film configured to form an amalgam with detected mercury. A mercury collection unit is configured to receive into a chamber a sample of a gas containing mercury, wherein the mercury collection unit is further configured to permit passage of portions of the mercury sensor tape through the chamber containing the gas sample so that the amalgam is formed with the thin metallic film. A mercury analysis unit includes a total reflection x-ray fluorescence (“TXRF”) system configured to perform a TXRF analysis of the amalgam, wherein the mercury analysis unit is configured to permit passage of the mercury sensor tape within a proximity of an XRF detector of the TXRF system.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: March 1, 2022
    Assignee: UHV Technologies, Inc.
    Inventors: Nalin Kumar, Manuel Gerardo Garcia, Jr.
  • Patent number: 11249113
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Patent number: 11204312
    Abstract: Full wafer in-situ metrology chambers and methods of use are described. The metrology chambers include a substrate support and a sensor bar that are rotatable relative to each other. The sensor bar includes a plurality of sensors at different radii from a central axis.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: December 21, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ami Sade, Todd Egan, Shay Assaf, Jacob Newman
  • Patent number: 11177183
    Abstract: A system includes a factory interface, a deposition tool, and at least one measuring device. The factory interface is configured to carry a wafer. The deposition tool is coupled to the factory interface and configured to process the wafer transferred from the factory interface. The at least one measuring device is equipped in the factory interface, the deposition tool, or the combination thereof. The at least one measuring device is configured to perform real-time measurements of a thickness of a material on the wafer that is carried in the factory interface or the deposition tool.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yan-Hong Liu, Chien-Chih Wu, Che-Fu Chen
  • Patent number: 11119059
    Abstract: According to one embodiment, a semiconductor defect inspection apparatus includes: an object-under-examination stage on which an inspection target object is placed; an X-ray irradiation unit that irradiates the object-under-examination stage with X-rays; an imaging unit that detects transmitted X-rays which passed through the inspection target object; a fluorescent X-ray detection unit that detects fluorescent X-rays which are emitted from the inspection target object by irradiation with the X-rays; and a defect detection unit that detects a first defect by an analysis of a transmission X-ray image which is obtained by performing photoelectric conversion of the transmitted X-rays and detects a second defect by a spectrum analysis of the fluorescent X-rays.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: September 14, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kiminori Yoshino
  • Patent number: 11079345
    Abstract: An X-ray inspection device of the present invention includes a sample placement unit 11 for placing a sample as an inspection target therein, a sample placement unit positioning mechanism 30 for moving the sample placement unit 11, a goniometer 20 including first and second rotation members 22, 23 that rotate independently of each other, an X-ray irradiation unit 40 installed on the first rotation member 22, and a two-dimensional X-ray detector 50 installed on the second rotation member 23. The sample placement unit positioning mechanism 30 includes a ? rotation mechanism 35 for rotating the sample placement unit 11 and a ?-axis about a ?-axis that is orthogonal to a ?s-axis and a ?d-axis at a measurement point P and extends horizontally.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 3, 2021
    Assignee: RIGAKU CORPORATION
    Inventors: Naoki Matsushima, Kiyoshi Ogata, Kazuhiko Omote, Sei Yoshihara, Yoshiyasu Ito, Hiroshi Motono, Hideaki Takahashi, Akifusa Higuchi, Shiro Umegaki, Shigematsu Asano, Ryotaro Yamaguchi, Katsutaka Horada
  • Patent number: 11011490
    Abstract: An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: May 18, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Rabih Khazaka, Benoît Thollin
  • Patent number: 10957609
    Abstract: A method includes performing Chemical Mechanical Polish (CMP) on a wafer, placing the wafer on a chuck, performing a post-CMP cleaning on the wafer, and determining cleanness of the wafer when the wafer is located on the chuck.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ting Yen, Chi-Ming Tsai, Hui-Chi Huang
  • Patent number: 10928418
    Abstract: A scanning probe microscope with a first actuator (3) configured to move a feature in the form of a tip (2) so that the feature follows a scanning motion. A vision system (10) is configured to collect light from a field of view to generate image data. The field of view includes the feature and the light from the field of view travels from the feature to the vision system via the steering element (13). A tracking control system (15)bis configured to generate one or more tracking drive signals in accordance with stored reference data. A second actuator (14) is configured to receive the one or more tracking drive signals and move the steering element on the basis of the one or more tracking drive signals so that the field of view follows a tracking motion which is synchronous with the scanning motion and the feature remains within the field of view.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 23, 2021
    Assignee: INFINITESIMA LIMITED
    Inventors: Andrew Humphris, David Gray
  • Patent number: 10876979
    Abstract: Provided are a processing method, a processing apparatus and a processing program which can perform pole figure measurement continuously without overlapping of an angle a in a pole figure with the small number of times of ? scan, thereby enabling the efficient measurement. The processing method for determining conditions of pole figure measurement by X-ray diffraction, includes the steps of. receiving input of a diffraction angle 2?; and determining an angle ? formed by an incident X-ray and an x-axis, and a tilt angle ? of a sample in each ? scan for a rotation angle ? within a sample plane so as to make a range of an angle a continuous from ?=90° to ?=0° without overlapping, the angle ? being formed by the sample plane and a scattering vector, the range of the angle ? are detectable at a time on a two-dimensional detection plane in the pole figure measurement at the diffraction angle 2?, in which determining the angle ? and the tilt angle ? is repeated.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: December 29, 2020
    Assignee: RIGAKU CORPORATION
    Inventors: Hisashi Konaka, Akihiro Himeda, Toru Mitsunaga, Keigo Nagao
  • Patent number: 10871515
    Abstract: Provided is a method of measuring the Fe concentration in a p-type silicon wafer by the SPV method, by which the detection limit for the Fe concentration can be lowered, and the measurement can be performed in a short time. The measurement by the SPV method is performed in a measurement mode in which irradiation with a plurality of lights having mutually different wavelengths is performed during the same period under conditions where (i) Time Between Readings is 35 ms or more and 120 ms or less and Time Constant is 20 ms or more, or Time Between Readings is 10 ms or more and less than 35 ms and Time Constant is 100 ms or more, and (ii) Number of Readings is 12 times or less.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: December 22, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Shinya Fukushima, Masahiko Mizuta
  • Patent number: 10867873
    Abstract: A method and a device for measuring a plurality of semiconductor chips in a wafer array are disclosed. In an embodiment a method for measuring the semiconductor chips in a wafer array, wherein the wafer array is arranged on an electrically conductive carrier so that in each case back contacts of the semiconductor chips are contacted by the carrier, wherein a contact structure is arranged on a side of the wafer array facing away from the carrier, and wherein the contact structure includes a contact element and/or a plurality of radiation-emitting measurement semiconductor chips, includes applying a voltage between the contact structure and the carrier and measuring the semiconductor chips depending on a luminous image which is generated by emitted radiation which is caused simultaneously by fluorescence when the semiconductor chips are illuminated or by a radiation-emitting operation of the measurement semiconductor chips when the voltage is applied.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 15, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Holger Specht, Roland Zeisel, Anton Vogl, Jens Ebbecke
  • Patent number: 10854384
    Abstract: A multilayer ceramic electronic component includes: a ceramic body including a dielectric layer and first and second internal electrodes alternately exposed to first and second outer surfaces with the dielectric layer interposed therebetween; and first and second external electrodes disposed on the first and second outer surfaces of the ceramic body so as to be connected to the first and second internal electrodes, respectively. The first internal electrode has a plurality of first ends connected to the first external electrode and a first recessed region positioned between the plurality of first ends, the first recessed region at least partially filled with a dielectric material. The second internal electrode has a plurality of second ends connected to the second external electrode and a second recessed region positioned between the plurality of second ends, the second recessed region at least partially filled with the dielectric material.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sun Cheol Lee, Gi Seok Jeong, Ho In Jun
  • Patent number: 10801976
    Abstract: A method for displaying measurement results from X-ray diffraction measurement, in which a sample is irradiated with X-rays and the X-rays diffracted by the sample are detected by an X-ray detector, comprises: (1) forming a one-dimensional diffraction profile by displaying, on the basis of output data from an X-ray detector, a profile in which one orthogonal coordinate axis shows 2? angle values and another orthogonal coordinate axis shows X-ray intensity values; (2) forming a two-dimensional diffraction pattern by linearly displaying X-ray intensity data, for each 2? angle value and on the basis of output data from the X-ray detector; the X-ray intensity data being present in the circumferential direction of a plurality of Debye rings formed at each 2? angle by diffracted X-rays; and (3) displaying the two-dimensional diffraction pattern and the one-dimensional diffraction profile so as to be aligned such that the 2? angle values of both coincide with each other.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 13, 2020
    Assignee: RIGAKU CORPORATION
    Inventors: Akito Sasaki, Akihiro Himeda, Yukiko Ikeda, Keigo Nagao
  • Patent number: 10790206
    Abstract: Testing structures, and their fabrication methods and testing methods are provided. An exemplary testing structure includes a base substrate containing a well region; a first doped epitaxial region in the well region and having a doping type same as a doping type of the well region; a dielectric layer on the base substrate and covering the well region and the first doped epitaxial region; a first contact plug passing through the dielectric layer and electrically connected with the first well region; and a second contact plug and a third contact plug. The second contact plug and the third contact plug pass through the dielectric layer and electrically connected with the first doped epitaxial region. The second contact plug is independent from the third contact plug and between the first contact plug and the third contact plug.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 29, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10739275
    Abstract: Disclosed is apparatus for inspecting a sample. The apparatus includes illumination optics for simultaneously directing a plurality of incident beams at a plurality of azimuth angles towards a sample and collection optics for directing a plurality of field portions of output light from two or more of the plurality of angles towards two or more corresponding sensors. The two or more sensors are arranged for receiving the field portions corresponding to two or more angles and generating two or more corresponding images. The apparatus further comprises a processor for analyzing the two or more images to detect defects on the sample.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 11, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Guoheng Zhao, Sheng Liu, Ben-ming Benjamin Tsai
  • Patent number: 10720345
    Abstract: Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Myra McDonnell, Brennen K. Mueller, Chytra Pawashe, Daniel Pantuso, Paul B. Fischer, Lance C. Hibbeler, Martin Weiss
  • Patent number: 10682596
    Abstract: The application generally relates to digital Engine Integrity Protection (EIP) systems for filters for internal combustion engines and methods of using the digital EIP systems. A pre-programmed digital chip is integrated in filtration hardware such that the Engine Control Unit (ECU) or another controller installed on the engine or vehicle can read encrypted digital signal from the chip when electrically connected with the filter hardware. Based on the read information from the chip, the ECU or controller can determine whether the filter associated with the chip is a genuine filter or a non-genuine filter.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 16, 2020
    Assignee: CUMMINS FILTRATION IP, INC.
    Inventors: Abhijit Shimpi, Andry Lesmana, Adaeze Okoye, Joseph Okoro
  • Patent number: 10669210
    Abstract: Provided is a large-sized silicon nitride sintered substrate and a method for producing the same. The silicon nitride sintered substrate has a main surface 101a of a shape larger than a square having a side of a length of 120 mm. A ratio dc/de of the density dc of the central area and the density de of the end area of the main surface 101a is 0.98 or higher. The void fraction vc of the central area of the main surface 101a is 1.80% or lower, and the void fraction ve of the end area is 1.00% or lower. It is preferred that the density dc of the central area is 3.120 g/cm3 or higher, the density de of the end area is 3.160 g/cm3 or higher, and a ratio ve/vc of the void fraction vc of the central area and the void fraction ve of the end area is 0.50 or higher.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 2, 2020
    Assignee: HITACHI METALS, LTD.
    Inventors: Hisayuki Imamura, Suguru Fujita, Youichirou Kaga, Hiroyuki Teshima, Shigeyuki Hamayoshi
  • Patent number: 10636583
    Abstract: A system may include a controller configured to cause a capacitance probe to subject a material to a first electric signal having a first frequency and determine a first capacitance of the material at the first frequency. The controller is configured to cause the capacitance probe to subject the material to a second electric signal at a second frequency and determine a second capacitance of the material at the second frequency. The material includes at least a first constituent phase and a second constituent phase. The first constituent phase and the second constituent phase have substantially similar dielectric constants at the first frequency and substantially different dielectric constants at the second frequency. The controller is further configured to determine a porosity of the material based on the first capacitance and determine a relative phase composition of the first constituent phase and the second constituent phase based on the second capacitance.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 28, 2020
    Assignee: Rolls-Royce Corporation
    Inventor: Michael George Glavicic
  • Patent number: 10614338
    Abstract: Methods and systems for descriptor guided fast marching method based image analysis and associated systems are disclosed. A representative image processing method includes processing an image of a microelectronic device using a fast marching algorithm to obtain arrival time information for the image. The arrival time information is analyzed using a targeted feature descriptor to identify targeted features. The detection of defects is facilitated by segmenting the image. The segmented image can be analyzed to identify targeted features which are then labeled for inspection.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Hong Chen
  • Patent number: 10599043
    Abstract: Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: March 24, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hiroyuki Ogiso, Jianhua Zhou, Zonghui Su, Juan Carlos Rocha-Alvarez, Jeongmin Lee, Karthik Thimmavajjula Narasimha, Rick Gilbert, Sang Heon Park, Abdul Aziz Khaja, Vinay Prabhakar
  • Patent number: 10586318
    Abstract: A method includes obtaining data associated with an electronic component. The method also includes conducting a multi-tier inspection process to verify a conformance of the electronic component. Each of the tiers includes a different type of identification test, and at least one of the tiers is configured to provide fuzzy outputs. The method further includes analyzing the data associated with the electronic component using one or more first tests associated with a first of the tiers to determine whether the electronic component conforms to a pre-specified requirement. In addition, the method includes generating an output based on the analysis and determining whether additional testing is required using one or more next-level tests associated with another of the tiers.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: March 10, 2020
    Assignee: Raytheon Company
    Inventors: Kristen Stone, Alexandra Cintron-Aponte, Blair Simons
  • Patent number: 10551166
    Abstract: Apparatus and methods for performing optically based film thickness measurements of highly absorbing films (e.g., high-K dielectric films) with improved measurement sensitivity are described herein. A highly absorbing film layer is fabricated on top of a highly reflective film stack. The highly reflective film stack includes one or more nominally identical sets of multiple layers of different, optically contrasting materials. The highly reflective film stack gives rise to optical resonance in particular wavelength ranges. The high reflectance at the interface of the highly absorbing film layer and the highly reflective film stack increases measured light intensity and measurement sensitivity. The thickness and optical dispersion of the different material layers of the highly reflective film stack are selected to induce optical resonance in a desired wavelength range. The desired wavelength range is selected to minimize absorption by the highly absorbing film under measurement.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: February 4, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Carlos L. Ygartua, Shankar Krishnan
  • Patent number: 10518700
    Abstract: An intrusion detection system and methods thereof are provided. In exemplary embodiments, the system may comprise an upper scanner adapted to create a first detection layer; a lower scanner adapted to create a second detection layer, the second detection layer overlapping the first detection layer; signal lighting for producing a visual signal; at least one server adapted analyze data received from the upper scanner and the lower scanner to determine if an object is in the path of the vehicle; and wherein the at least one server is adapted to activate the signal lighting when it is determined by the server that an object is in the path of the vehicle.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 31, 2019
    Inventors: George Engel, David Engel
  • Patent number: 10510623
    Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Wei Fang, Jing-Sen Wang, Yuan-Yao Chang, Wei-Ray Lin, Ting-Hua Hsieh, Pei-Hsuan Lee, Yu-Hsuan Huang
  • Patent number: 10458912
    Abstract: Methods and systems for performing optical, model based measurements of a small sized semiconductor structure employing an anisotropic characterization of the optical dispersion properties of one or more materials comprising the structure under measurement are presented herein. This reduces correlations among geometric parameters and results in improved measurement sensitivity, improved measurement accuracy, and enhanced measurement contrast among multiple materials under measurement. In a further aspect, an element of a multidimensional tensor describing the dielectric permittivity of the materials comprising the structure is modelled differently from another element. In a further aspect, model based measurements are performed based on measurement data collected from two or more measurement subsystems combined with an anisotropic characterization of the optical dispersion of the materials under measurement.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: October 29, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Houssam Chouaib, Qiang Zhao, Andrei V. Shchegrov, Zhengquan Tan
  • Patent number: 10446563
    Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: October 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiang-Zheng Bo, John H. Macpeak, Douglas T. Grider
  • Patent number: 10361102
    Abstract: A cutting apparatus includes a cutting unit including a cutting blade that has a cutting edge for cutting a dresser board. An elastic wave detection sensor is disposed in the cutting unit, for detecting an elastic wave produced when the dresser board is cut. The elastic wave detection sensor produces an output signal representing the detected elastic wave when the cutting blade cuts the dresser board and is dressed thereby, the output signal being variable as the cutting blade is progressively dressed by the dresser board. A control unit stores in advance, as a threshold value, the value of the output signal when the dressing of the cutting blade is completed. The control unit stops cutting the dresser board with the cutting blade and finishes the dressing of the cutting blade when the output signal produced by the elastic wave detection sensor reaches the threshold value.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 23, 2019
    Assignee: DISCO CORPORATION
    Inventors: Takuya Kaminaga, Tomoaki Sugiyama, Saki Miyakawa
  • Patent number: 10346966
    Abstract: A non-destructive inspection method that comprises obtaining one or more images corresponding to an X-ray, scanning electron microscope, or CT scan of an object, assigning numeric values to pixels of the images, comparing the numeric values to reference numeric values, and identifying an anomaly in the object based on the comparison. A non-destructive inspection system that comprises at least one processor, a memory in communication with the processor and storing instructions that causes the processor to obtain an image corresponding to an X-ray, scanning electron microscope, or CT scan of an object, assign numeric values to pixels of the image, compare the assigned numeric values to reference numeric values, and identify an anomaly in the object based on the comparison.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 9, 2019
    Assignee: HALLIBURTON ENERGY SERVICES, INC.
    Inventors: Corbin Sean Glenn, Zhenyu Xue
  • Patent number: 10339262
    Abstract: A method includes identifying a first set of a first care area with a first sensitivity threshold, the first care area associated with a first design of interest within a block of repeating cells in design data; identifying an additional set of an additional care area with an additional sensitivity threshold, the additional care area associated with an additional design of interest within the block of repeating cells in design data; identifying one or more defects within the first set of the first care areas in one or more images of a selected region of a sample based on the first sensitivity threshold; and identifying one or more defects within the additional set of the additional care areas in the one or more images of the selected region of the sample based on the additional sensitivity threshold.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: July 2, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Junqing Huang, Soren Konecky, Hucheng Lee, Kenong Wu, Lisheng Gao
  • Patent number: 10338009
    Abstract: A method and apparatus to measure specular reflection intensity, specular reflection angle, near specular scattered radiation, and large angle scattered radiation and determine the location and type of defect present in a first and a second transparent solid that have abutting surfaces. The types of defects include a top surface particle, an interface particle, a bottom surface particle, an interface bubble, a top surface pit, and a stain. The four measurements are conducted at multiple locations along the surface of the transparent solid and the measured information is stored in a memory device. The difference between an event peak and a local average of measurements for each type of measurement is used to detect changes in the measurements. Information stored in the memory device is processed to generate a work piece defect mapping indicating the type of defect and the defect location of each defect found.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: July 2, 2019
    Assignee: KLA-TENCOR CORPORATION
    Inventors: Steven W. Meeks, Ronny Soetarman
  • Patent number: 10325796
    Abstract: An apparatus includes a holder configured to carry one or more semiconductor wafers, an arm coupled with the holder, and a detector coupled with either the holder or the arm. The detector is configured to measure a change in weight of the one or more semiconductor wafers. The detector includes a strain gauge weight sensor, a piezoelectric sensor, or any other suitable sensor. The change in weight of the one or more semiconductor wafers is used to determine any possible presence of a broken or missing wafer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng Chen, Yan Cing Lin, Chui-Ya Peng
  • Patent number: 10283420
    Abstract: The invention is directed to a method for the production of an optoelectronic module including a support (5) and an additional layer, said support being formed by an assembly (25) which has no optoelectronic properties and which comprises, successively, a metal substrate (27), a dielectric coating (29) disposed on the metal substrate, and an electrically conductive layer (31) disposed on the dielectric coating. The production method comprises: a step of providing the support and performing a method in which the support is checked, or providing the support after it has already been checked; and a step of depositing at least one additional layer on the electrically conductive layer.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: May 7, 2019
    Assignee: ArcelorMittal
    Inventor: Philippe Guaino