Abstract: A method for making a cadmium sulfide layer is provided. The method includes a number of steps including providing a substrate and disposing a layer containing cadmium on the substrate followed by sulfurization of the cadmium-containing layer.
Type:
Grant
Filed:
November 22, 2010
Date of Patent:
February 21, 2012
Assignee:
General Electric Company
Inventors:
Bastiaan Arie Korevaar, Scott Feldman-Peabody, Robert Dwayne Gossman
Abstract: A method for forming a shallow trench isolation (STI) structure with a predetermined target height is provided. A substrate having a pad oxide layer formed on the substrate is provided. A nitride-containing layer with a thickness is formed on the pad oxide. A STI structure is formed and extends through the nitride-containing layer, the pad oxide layer, into the substrate. The thickness of the nitride-containing layer is measured to calculate the height of STI structure according to a correlation between the thickness of the nitride-containing layer and the height of STI structure. A thickness of the top portion STI structure to be removed is determined according to the difference between the height of the STI structure and the predetermined target height and is removed in a first etching process. The nitride-containing layer is removed without etching the STI structure or the pad oxide layer in a second etching process.
Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPDX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPDX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
Type:
Application
Filed:
May 24, 2010
Publication date:
January 6, 2011
Inventors:
Woong-Hee SOHN, Gil-Heyun CHOI, Byung-Hee KIM, Byung-Hak LEE, Tae-Ho CHA, Hee-Sook PARK, Jae-Hwa PARK, Geum-Jung SEONG
Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.
Type:
Application
Filed:
June 14, 2010
Publication date:
December 2, 2010
Applicant:
Hynix Semiconductor Inc.
Inventors:
Cha Deok DONG, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee