Trench Shape Altered By Local Oxidation Of Silicon Process Step, E.g., Trench Corner Rounding By Locos (epo) Patents (Class 257/E21.55)
-
Publication number: 20080315352Abstract: A method of manufacturing a semiconductor device begins when a first dielectric pattern is formed on and/or over a substrate, and a first etching process is performed to form a trench in the substrate. An edge portion of the first trench is exposed. An oxidation process is performed on and/or over the substrate rounding the edge portion of the trench. A second dielectric is formed on and/or over the substrate including the trench, and a planarization process is performed on the second dielectric. A photoresist pattern is formed on and/or over the second dielectric corresponding to the trench, and a second etching process is performed to form a second dielectric pattern filling the trench. The photoresist pattern is removed. A second cleaning process is performed on the substrate including the trench to form a device isolation layer, which is formed by removing a portion of the second dielectric pattern.Type: ApplicationFiled: June 17, 2008Publication date: December 25, 2008Inventor: Hyun-Ju Lim
-
Publication number: 20080299740Abstract: A method for forming a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate, having a trench-like opening therein exposing a portion of the substrate. A thermal oxidation process is performed to the substrate. An anisotropic etching process is performed using the patterned mask layer as a mask to form a trench in the substrate, and then the trench is filled with an insulating material.Type: ApplicationFiled: May 29, 2007Publication date: December 4, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hui-Ying Tsai, Cheng-Ming Yih
-
Patent number: 7453134Abstract: An integrated circuit device has a substrate with first and second portions. One or more first active regions are formed in the first portion of the substrate. Each of the one or more first active regions has rounded corners. One or more first circuit elements are formed on the one or more first active regions after the corners of the one or more first active regions have been rounded. One or more second active regions are formed in the second portion of the substrate. One or more second circuit elements are formed on the one or more second active regions.Type: GrantFiled: January 12, 2007Date of Patent: November 18, 2008Assignee: Micron Technology, Inc.Inventors: Sukesh Sandhu, Kevin Torek
-
Patent number: 7436030Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.Type: GrantFiled: August 10, 2006Date of Patent: October 14, 2008Assignee: International Business Machines CorporationInventors: Haining Yang, Thomas W. Dyer, Wai-Kin Li
-
Patent number: 7405461Abstract: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.Type: GrantFiled: September 7, 2005Date of Patent: July 29, 2008Assignee: Sanyo Electric Co., Ltd.Inventor: Haruki Yoneda
-
Patent number: 7396729Abstract: A semiconductor device is formed by providing a substrate. A trench is formed in the substrate. Beveled surfaces are formed at upper portions of sidewalls of the trench opposite a bottom surface of the trench, respectively. An oxide layer is formed in the trench such that the oxide layer is thicker on the beveled surfaces of the trench than on other surfaces of the trench.Type: GrantFiled: August 31, 2005Date of Patent: July 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Chul Jeong, Wook-Hyoung Lee
-
Patent number: 7390717Abstract: A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.Type: GrantFiled: February 9, 2005Date of Patent: June 24, 2008Assignee: International Rectifier CorporationInventors: Jianjun Cao, Paul Harvey, David Kent, Robert Montgomery, Kyle Spring
-
Patent number: 7391096Abstract: An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An oxide and a second nitride layer are deposited on the surface of the substrate including the trench. A spacer is formed on the lateral walls of the trench by etching the second nitride layer. A buried oxide is grown in the substrate underneath the trench by performing thermal oxidation on the substrate. The trench is then filled by depositing an insulating layer after removing the spacer and performing a planarization process. The STI fabricating method can reduce substantially a total parasitic capacitance. Therefore, gate RC delay is reduced and the operating speed of a transistor increases.Type: GrantFiled: December 1, 2005Date of Patent: June 24, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
-
Patent number: 7358587Abstract: In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and comprising an upper corner at a periphery of the opening, the upper corner having a corner angle with a first degree of sharpness; b) reducing the sharpness of the corner angle to a second degree; c) after reducing the sharpness, forming a layer of material within the opening and over the etch-stop layer; and d) planarizing the material with a method selective for the material relative to the etch-stop layer to remove the material from over the etch-stop layer while leaving the material within the opening.Type: GrantFiled: April 25, 2005Date of Patent: April 15, 2008Assignee: Micron Technology, Inc.Inventors: John T. Moore, Guy T. Blalock
-
Patent number: 7339252Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second mesas. The method also includes oxidizing sidewalls and bottoms of each trench; depositing a doped oxide into each trench and on the tops of the first and second mesas; and thermally oxidizing the semiconductor substrate at a temperature sufficient enough to cause the deposited oxide to flow so that the silicon in each of the first mesas is completely converted to silicon dioxide while the silicon in each of the second mesas is only partially converted to silicon dioxide and so that each of the trenches is filled with oxide.Type: GrantFiled: March 20, 2006Date of Patent: March 4, 2008Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Richard A. Blanchard
-
Patent number: 7279396Abstract: The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to form an isolation trench within semiconductive material of the semiconductor substrate. A trench isolation material is formed within the isolation trench and over the masking material outside of the trench effective to overfill the isolation trench. The trench isolation material is polished at least to an outermost surface of the at least one of tungsten, titanium nitride and amorphous carbon of the masking material. The at least one of tungsten, titanium nitride and amorphous carbon is/are etched from the substrate. Other implementations and aspects are contemplated.Type: GrantFiled: August 22, 2005Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, H. Montgomery Manning
-
Patent number: 7273792Abstract: A semiconductor device including a semiconductor substrate, a device isolation region formed by filling a trench in the semiconductor substrate with dielectric material and defining device regions in the semiconductor substrate. The trench has a rounded upper edge, and a dummy thin layer formed on the rounded upper edge.Type: GrantFiled: December 30, 2004Date of Patent: September 25, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Yong Keon Choi
-
Patent number: 7223698Abstract: A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.Type: GrantFiled: February 10, 2005Date of Patent: May 29, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Douglas J. Bonser, Srikanteswara Dakshina-Murthy, Mark C. Kelling, John G. Pellerin, Johannes F. Groschopf, Edward Asuka Nomura
-
Patent number: 7172910Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to forming an assembly using different sized blocks in either a flexible or rigid substrate.Type: GrantFiled: June 28, 2005Date of Patent: February 6, 2007Assignee: Alien Technology CorporationInventors: Mark A. Hadley, Ann Chiang, Gordon S. W. Craig, Jeffrey Jay Jacobsen, John Stephen Smith, Jay Tu, Roger Green Stewart
-
Patent number: 7154159Abstract: A trench isolation structure and a method of forming a trench isolation structure are provided. The method includes providing a substrate having a trench. A polysilicon liner is formed in the trench. A dielectric layer, such as spin-on glass, is formed in the trench upon the polysilicon liner.Type: GrantFiled: February 24, 2004Date of Patent: December 26, 2006Assignee: Nanya Technology CorporationInventors: Chien-Chang Cheng, Shing-Yih Shih, Chang-Rong Wu
-
Patent number: 6887767Abstract: A method for manufacturing a semiconductor device including forming a buffer film on a semiconductor substrate, forming a element partitioning trench, forming a oxidized film on the surface of the element partitioning trench, and washing the semiconductor substrate with hydrofluoric acid. The washing removes part of the buffer film, and the end of the buffer film is inwardly removed from the top edge of the element partitioning trench by a predetermined distance. The distance and the thickness of the oxidized film are represented by the expression 0?x?(d/2 sin ?), where x represents the distance, and ? represents the angle between a plane parallel to the semiconductor substrate and a side surface of the element partitioning trench.Type: GrantFiled: March 21, 2003Date of Patent: May 3, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Mayumi Nakasato, Kazuhiro Sasada, Masahiro Oda
-
Patent number: 6713780Abstract: A method of providing a substantially planar trench isolation region having substantially rounded corners, said method comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a nitride layer; (b) patterning said film stack to form at least one trench within said substrate, wherein said patterning exposes sidewalls of said oxide layer, polysilicon layer and nitride layer; (c) oxidizing the at least one trench and said exposed sidewalls of said oxide layer and said polysilicon layer so as to thermally grow a conformal oxide layer in said trench and on said exposed sidewalls of said oxide layer and said polysilicon layer; (d) filling said trench with a trench dielectric material; and (e) planarizing to said surface of said substrate.Type: GrantFiled: December 21, 2001Date of Patent: March 30, 2004Assignee: International Business Machines CorporationInventor: Chung Hon Lam