Abstract: A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect.

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: A semiconductor packaging structure is provided. The structure includes a base layer comprising alloy 42; die attached on a first side of the base layer; and an interconnect structure on the die, wherein the interconnect structure comprises vias and conductive lines connected to the die.

Abstract: A semiconductor device of the present invention includes: a plurality of semiconductor chips each having a chip size package structure; and a substrate bonded via an adhesive material to an opposite surface in each of the plurality of semiconductor chips that is opposite to a connection surface that is provided with solder balls (external connection terminals). Thereby, the plurality of semiconductor chips are connected to each other.

Abstract: A 3D circuit module which is highly reliable, easily layered and able to mount electronic components in high density is obtained by providing a support member having a frame in the periphery thereof and a recess; a coating layer for coating the frame and filling in the recess, the coating layer being made of resin material which is adhesive and has a softening temperature lower than the softening temperature of the support member; a wiring pattern formed on the coating layer, the wiring pattern including a first land on the frame, a second land on the recess, and a wiring part for connecting between the first land and the second land; and an electronic component having a projecting electrode formed on a side thereof, the electronic component being bonded to the coating layer and accommodated in the recess, with the projecting electrode connected to the second land.

Abstract: In order to implement a high-density high-performance semiconductor system small in size, there is provided a method for implementing three-dimensional connection between a plurality of semiconductor chips differing from each other with the shortest metal interconnect length, using penetration electrodes, thereby enabling a fast operation at a low noise level, the method being a three-dimensional connection method very low in cost, and short in TAT in comparison with the known example, capable of bonding at an ordinary temperature, and excellent in connection reliability.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also includes an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.

Abstract: A method for forming a molded circuit board is provided. The method includes the steps of forming a circuit having a first section and a second section on a conductive substrate, the first section and the second section being coplanar; then deforming the conductive substrate by mold-pressing, so that the first section and the second section become non-coplanar; providing a plastic material to cover the circuit and the conductive substrate; curing the plastic material by injection-molding; and removing the conductive substrate to expose the circuit. The molded circuit board made by this method is also provided.

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. In an embodiment of the present invention, the method of manufacturing a printed circuit board can include: providing a pair of conductive layers, in which roughness of one surface of one of the pair of conductive layers is different from roughness of one surface of the other of the pair of conductive layers; and stacking the pair of the conductive layers on a dielectric layer such that one surface of one of the pair of conductive layers faces one surface of the dielectric layer and one surface of the other of the pair of conductive layers faces another surface of the dielectric layer.

Abstract: An electronic component includes an electronic element, a conductive first base portion, a conductive second base portion, an insulator and a terminal. An electronic element is to be mounted on the electronic element mounting portion. The electronic element mounting portion is mounted on the first base portion. The insulator insulates the first base portion from the second base portion and couples the first base portion to the second base portion. The terminal is provided on the first base portion and is insulated from the first base portion.

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: Methods are disclosed for providing reduced particle generating silicon carbide. The silicon carbide articles may be used as component parts in apparatus used to process semiconductor wafers. The reduced particle generation during semiconductor processing reduces contamination on semiconductor wafers thus increasing their yield.

Abstract: A leadless semiconductor package mainly includes a plurality of inner leads, a chip pad, a semiconductor chip and a molding compound. A non-conductive ink is filled between every two of the inner leads, and couples the inner leads to the chip pad so as to be in replacement of the conventional tie bars. The semiconductor chip is disposed on the chip pad and electrically connected to the inner leads. Moreover, the molding compound is formed on the inner leads and the non-conductive ink for encapsulating the semiconductor chip. The non-conductive ink prevents the exposed bottom surfaces of the inner leads from contamination by the molding compound without attaching an external tape during molding. Also the inner leads can be in a multi-row arrangement and the chip pad can be disposed in an optional location.

Abstract: In a semiconductor module including multiple semiconductor devices, a signal that flows through a bonding wire connected to one semiconductor device is prevented from acting as noise which affects another semiconductor device, thereby improving the operation reliability of the semiconductor module. A second semiconductor device provided alongside a first semiconductor device includes a current output electrode via which large current is output. The current output electrode is electrically connected to a substrate electrode provided to a first wiring layer via a bonding wire such as a gold wire. The bonding wire is provided across the side E2 of the second semiconductor device. The bonding wire connected to the first semiconductor device is provided across a side of the first semiconductor device that corresponds to the side El of the second semiconductor device, i.e., the side F2, F3, or F4 of the first semiconductor device.

Abstract: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.

Abstract: To pick and place standard dice on a new base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type wafer level package. Moreover, the die may be packaged with passive components or other dice with a side by side structure or a stacking structure.

Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.

Abstract: A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the first cavity and the second cavity, having an active surface with a plurality of electrode pads thereon; and one built-up structure disposed on the surface of the first aluminum substrate and the active surface of the chip, wherein the built-up structure has a plurality of conductive vias electrically connecting to the electrode pads. The substrate warpage is obviously reduced by the assistance of using aluminum or aluminum alloy as the material of the substrate. Also, a method of manufacturing a packaging substrate having a chip embedded therein is disclosed.

Abstract: Methods for singulating surface-mountable semiconductor devices and for fitting external contact areas to the devices are described herein. Semiconductor device components are applied to a metallic carrier in rows and columns in corresponding semiconductor device positions of the metallic carrier. Thereafter, a plurality of components, situated in the device positions, is embedded into a plastic housing composition, thereby producing a composite board. The composite board is subsequently separated into individual semiconductor devices by laser ablation, the semiconductor devices being inscribed on their top sides via the laser technique. The top sides with the inscription can then be adhesively bonded to an adhesive film, so that the undersides of the devices can be uncovered while maintaining the semiconductor device positions.

Abstract: A method of producing a leadframe is provided, the method including the steps of providing a substrate, plating the substrate with a layer of tin, plating a layer of nickel over the layer of tin, and thereafter plating one or more protective layers over the layer of nickel. The leadframe may thereafter be heated to produce one or more intermetallic layers comprising tin, which impedes the out-diffusion of copper from a base material of the leadframe to the surface thereof.

Abstract: Provided are semiconductor die flip chip packages with warpage control and fabrication methods for such packages. A package includes a heat spreader that is attached to a die and a stiffener, which are in turn attached to a package substrate. In general, the stiffener is made of a material that has a relatively low CTE value. For example, the stiffener material may have a CTE value less than 12 ppm/° C. The material may also have a relatively low mass density value of less than 8.9 g/cm3. Such a material may include natural graphite or some composite form of it. The result is a package with less bowing and so improved co-planarity (e.g., in compliance with industry specifications) with the surface to which it is ultimately bound; thereby, improving the reliability of the package. Moreover, a package that is relatively lighter and more robust than conventional semiconductor die flip chip packages can be realized.

Abstract: A base substrate for chip scale package includes a carrier member made of electrical conductive metals with a first through opening; an active member laminated by a base layer made of electrical conductive metal and an intermediate layer made of electrical insulating or dielectric material, the active member having a through opening with a diameter larger that the diameter of the through opening of the base metal member; the active member being coupled with the carrier member in such a way that the intermediate layer is adhered to an upper surface of the carrier member, and these through openings are aligned to define a shoulder around the through opening of the base metal plate.

Abstract: A method for manufacturing an adhesive substrate with a die-cavity sidewall is disclosed. A region for forming die-cavity sidewall is defined on one surface of the substrate. The substrate is laminated with a sacrificial film, a partially cured resin is formed between the substrate and the sacrificial film. And then, an aperture is routed through the substrate, the partially cured resin, and the sacrificial film. The aperture is located corresponding to the region so that the substrate has a die-cavity sidewall formed inside the aperture. Thereafter, the sacrificial film is removed to expose the partially cured resin on the substrate so that the substrate with a die-cavity sidewall can have good adhesion.

Abstract: A release film for soft composite materials is provided. The release film contains a film with a closely packed self-assembled monolayer. A method of applying soft composite materials to a substrate without loss of the soft composite material to the release film is also provided. The method is useful in applications such as applying thermal pastes to semiconductor packaging.

Abstract: A semiconductor element heat dissipating member is provided which has excellent heat dissipation characteristics and adhesion characteristics and enables production of a semiconductor device at a low cost. A semiconductor device using the same, and a method of producing the same are also provided. The semiconductor element heat dissipating member has a conductive substrate and an electrically insulating amorphous carbon film containing hydrogen, and the electrically insulating amorphous carbon film is formed at least on a region of the conductive substrate on which region a semiconductor element is to be mounted.

Abstract: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.

Abstract: An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. A die is positioned above the surface of portions of a pair of flex circuits. Connection is made between the die and the flex circuitry. A protective layer is formed to protect the flex-connected die and its connection to the flex. Connective elements are placed along the flex circuitry to create an array of module contacts along the second side of the flex circuitry. The flex circuitry is positioned above the body-protected die to create an integrated lower stack element. The integrated lower stack element may be stacked either with iterations of the integrated lower stack element or with a pre-packaged IC to create a multi-element stacked circuit module.

Abstract: A semiconductor device of the present invention includes: a plurality of semiconductor chips each having a chip size package structure; and a substrate bonded via an adhesive material to an opposite surface in each of the plurality of semiconductor chips that is opposite to a connection surface that is provided with solder balls (external connection terminals). Thereby, the plurality of semiconductor chips are connected to each other.

Abstract: There is provided a method for producing a metal/ceramic bonding circuit board, which can form a fine pattern even if a circuit forming metal plate is thick and which can shorten the time required to carry out etching, when a molten metal is caused to contact to a ceramic substrate to be cooled and solidified to bond the circuit forming metal plate to the ceramic substrate to etch the circuit forming metal plate to form a metal circuit plate having a desired circuit pattern. A molten metal is caused to contact both sides of a ceramic substrate 10 to be cooled and solidified. Thus, a circuit forming metal plate 12 having a shape similar to a desired circuit pattern is bonded to one side of the ceramic substrate 10, and a metal base plate 14 is bonded to the other side thereof.

Abstract: A microelectronic assembly and a fabrication method are provided which includes a microelectronic element such as a chip or element of a package. A plurality of surface-mountable contacts are arranged in an array exposed at a major surface of the microelectronic element. One or more passive elements, e.g., a resistor, inductor, capacitor, or combination of the same are mounted to the microelectronic element, with an inner terminal of the passive element conductively mounted to an exposed surface of one contact and an outer terminal displaced vertically from the major surface of the microelectronic element.

Abstract: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.

Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).

Abstract: A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer. In some embodiments a row of wire bond sites on the land side of adjacent bond fingers is exposed by a common opening in the dielectric layer, providing for a finer pitch interconnect and, accordingly, a higher interconnect density between stacked packages. Also a land grid array package having such a single metal layer tape substrate.

Abstract: Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane.

Abstract: An electrical package and manufacturing method thereof is provided. A high stiffness, high electrical conductivity, low coefficient of thermal expansion and high thermal conductivity support substrate is used as an initial layer for building the package. A multilayer interconnection structure is formed over the support substrate. Thereafter, a plurality of openings is formed over the support substrate. The openings expose a plurality of bonding pads on a bottom surface of the multi-layer interconnection structure. An electronic device is set up over the multi-layer interconnection structure. Contacts are formed inside the opening over the bonding pads.