Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

Abstract: A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal includes conductors which function as an internal signal transmission system for the component, and a mask layer which functions as a solder mask and an outer insulating layer for the component. An adhesive layer in physical contact with the conductors attaches the circuit decal to the stiffener, and electrically insulates the conductors from the stiffener. The component also includes an area array of terminal contacts on the conductors electrically isolated by the mask layer. A method for fabricating the component includes the steps of attaching the circuit decal to the stiffener, attaching the die to the stiffener, interconnecting the die and the circuit decal, encapsulating the die, and forming the terminal contacts.

Abstract: The present invention provides a circuit board which prevents an adverse effect to be caused on electronic components by flux or the like that is produced at the time of soldering. According to this invention, land patterns 6 and 7 for connecting a flat cable 5 and a slide switch 4 are formed apart from each other on a circuit board and a slit 10 is formed between the land patterns 6 and 7. Consequently, although flux is produced when terminals 5a to 5f of the flat cable 5 are soldered to the land pattern 7, the flux can escape from the slit 10 and does not intrude into the slide switch 4 easily.

Abstract: A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

Abstract: A wiring board used for mounting an LED bare chip capable of firmly bonding the LED bare chip and improving yield. In a printed wiring board 2, a distance D between wiring patterns 81 and 85 disposed so as to oppose each other is the smallest at a position nearest to a center point (G) of an LED chip 14 disposed at a designed location, and increases with an increasing distance from the point G. In addition, pattern edges 83 and 87 of the wiring patterns 81 and 85 recede in the direction of widening the distance D as a distance from the center point G increases with respect to electrode edges 148 and 149 of the LED chip 14.

Abstract: A memory card is provided. The memory card comprises a substrate, a plurality of electronic package devices, a molding compound and a plastic forming material. The substrate has at least a plurality of outer contacts and a plurality of inner contacts and the outer contacts are electrically connected to the inner contacts. The electronic package devices are located on the substrate and the electronic package devices electrically connect to the inner contacts, respectively. The molding compound is covering the electronic package devices and the corresponding inner contacts. The plastic forming material is covering the molding compound and the substrate, and the plastic forming material exposes the outer contacts.

Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).

Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.

Abstract: Contact openings in semiconductor substrates are formed through insulative layers using an etchant material. The etchant typically leaves behind a layer of etch residue which interferes with the subsequent deposition of conductive material in the opening, as well as the conductive performance of the resulting contact. A method of etch removal from semiconductor contact openings utilizes ammonia to clean the surfaces thereof of any etch residue.