Abstract: Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.

Abstract: A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.

Abstract: In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN.

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.

Abstract: In accordance with the present invention, there is provided a semiconductor package or device including a uniquely configured leadframe sized and configured to maximize the available number of exposed lands in the semiconductor device. More particularly, the semiconductor device of the present invention includes a die pad (or die paddle) defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.

Abstract: Reliable electrical contact is made with electronic components and effective electrical isolation is produced between the top and bottom of the electronic components. An electronic component is arranged inside a window in a first layer on a substrate. Next, a second layer is put on such that contact areas on the component and contact points on the first layer are freely accessible. Electrical contacts and electrical connecting lines are produced by electrodeposition. The second layer is used to produce bridges over an interval range between the electronic component and the first layer. The bridges have connecting lines formed on them. The second layer can be removed again. Radio-frequency modules can be produced in compact fashion and can be combined with audio-frequency components.

Abstract: An LED includes a base, a first lead and a second lead mounted to the base, a light emitting chip electrically connected to the first lead and the second lead, and an encapsulant sealing the chip. The first lead and the second lead each include a first beam and a second beam connected to each other. Each of the first beam and the second beam has two opposite ends protruding beyond two opposite lateral faces of the base, respectively, for electrically connecting with a circuit board.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: A semiconductor device includes at least a die carried by a substrate, a plurality of bond pads disposed on the die, a plurality of conductive components, and a plurality of bond wires respectively connected between the plurality of bond pads and the plurality of conductive components. The plurality of bond pads respectively correspond to a plurality of signals, and include a first bond pad configured for transmitting/receiving a first signal and a second bond pad configured for transmitting/receiving a second signal. The plurality of conductive components include a first conductive component and a second conductive component. The first conductive component is bond-wired to the first bond pad, and the second conductive component is bond-wired to the second bond pad. The first conductive component and the second conductive component are separated by at least a third conductive component of the plurality of conductive components, and the first signal is asserted when the second signal is asserted.

Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.

Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Abstract: A semiconductor device and a manufacturing method for preventing mechanical and thermal damage to the semiconductor chip. A laser beam welds a first connection pad formed on a first external lead to a first electrode formed on the surface of the semiconductor chip. A first connection hole is formed in the first connection pad, and the first connection hole overlaps the first connection electrode. A laser beam irradiates an area including the first connection hole, and the first connection pad in a portion around the first connection hole is melted to form a melting section, that is welded to the first connection electrode to easily form a semiconductor device with more excellent electrical characteristics.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.

Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.

Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.

Abstract: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.

Abstract: An integrated circuit includes a substrate; a sealing element spanning a periphery of the substrate that forms a protective boundary for the substrate; a plurality of copper lines spanning the substrate in at least two distinct layers contained within the protective boundary; a first conducting element disposed outside the sealing element; and one or more second conducting elements connecting at least two of the copper lines and that spans the sealing element; wherein the conducting elements are substantially non-oxidizing metals that are resistant to oxidization and that connect the copper line to the first conducting element.

Abstract: An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangement of first and second electrically conductive bond fingers. These first and second bond fingers are elevated at first and second different heights, respectively, relative to the plurality of electrically conductive pads. The printed circuit board also includes a first plurality of electrically insulating pedestals supporting respective ones of the first electrically conductive bond fingers at elevated heights relative to the second electrically conductive bond fingers. First and second pluralities of electrical interconnects (e.g., wires, beam leads) are also provided.

Abstract: A method of expanding the contact pitch for un-diced chips in an array by pre-slicing the array in a first direction, attaching a lead frame to the chips' contacts, and then slicing the array and attached lead frame in the second direction. The lead frame has leads mechanically connected one another such that slicing the frame in the second direction along the mechanical connections separates the leads. Each lead has a first terminal which is conductively attached to a chip contact and a second terminal extending beyond the boundaries of the chip to which the first terminal is attached. In this manner, the contact pitch is effectively expanded to the terminal pitch of the leads.

Abstract: A flip-chip packaging substrate with gradational pad pitches for flip-chip jointing a bumped chip and a flip chip package utilizing the substrate are revealed. A plurality of connecting pads with non-equal pitches are disposed in an array on the substrate for jointing a plurality of equal-pitch bumps of a bumped chip. The pitches of the connecting pads are numbered according to the distance from a central line through a defined central point. When the defined pitch numbers increase by one, a substrate CTE compensation value is subtracted from the distance from the corresponding connecting pads to the center point so that the connecting pads are able to accurately align to the equal-pitch bumps during reflowing processes. Therefore, the expansion distance from the connecting pads of the substrate to the central point is equal to the expansion distance from the bumps of the bumped chip to the central point to avoid alignment shift between the bumps and the corresponding connecting pads due to CTE mismatch.

Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.

Abstract: A device includes a first device structure having a semiconductor platform, and a second device structure having a microstructure spaced from the semiconductor platform. The device further includes a cable having a plurality of beams to couple the microstructure to the first device structure. Each beam of the plurality of beams has a polymer coating and a serpentine-shaped region.

Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Through hole vias (THV) are formed in the die extension region. A conductive plane or ring is formed in a center area on the active surface of the semiconductor die. The conductive plane or ring is coupled to a first contact pad for providing a first power supply potential to the active circuits. The conductive plane or ring is electrically connected to a first THV. A conductive ring is formed partially around a perimeter of the conduction plane or ring. The conductive ring is coupled to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.

Abstract: A power semiconductor device has a semiconductor chip stack and lines within a housing. The lines electrically connect large-area contact regions of power semiconductor device components within the housing to one another. In this case, at least one of the lines has a large-area planar conductive layer. This planar conductive area electrically connects the large-area contact regions to one another.

Abstract: A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns 25 to 27 are formed. The heat dissipation patterns have a surface area broader than that of the lead patterns and have the heat dissipating electrode patterns disposed thereon.

Abstract: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.

Abstract: A method and device relating the electrical interconnection of angularly disposed conductive is disclosed. Conventional wire bonding equipment is used to apply a wire ball on a first conductive surface in an electronic assembly. A conductive wire is drawn up vertically and terminated such that the central portion of the wire is proximal the second conductive surface. The electronic assembly is reoriented with respect to the travel of the capillary whereby a stitch bond is defined upon the second conductive surface to define an interconnect wire and a terminal wire portion, which terminal wire portion is removed.

Abstract: Non-rectilinear routing in a rectilinear mesh. In accordance with an embodiment of the present invention, an integrated circuit comprises a first substantially continuous metallization layer. The first substantially continuous metallization layer further comprises first and second portions electrically isolated from one another. The integrated circuit includes a trace disposed between and electrically isolated from the first and second portions of the first substantially continuous metallization layer. The trace is not parallel to an edge of the integrated circuit.

Abstract: A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film. A portion of the passivation dielectric film is then etched away to form a reinforcement pattern on the inlaid metal wiring. The reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring. A conductive pad is formed over the reinforcement pattern and the passivation dielectric film. The conductive pad fills the inter-space of the reinforcement pattern.

Abstract: An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangement of first and second electrically conductive bond fingers. These first and second bond fingers are elevated at first and second different heights, respectively, relative to the plurality of electrically conductive pads. The printed circuit board also includes a first plurality of electrically insulating pedestals supporting respective ones of the first electrically conductive bond fingers at elevated heights relative to the second electrically conductive bond fingers. First and second pluralities of electrical interconnects (e.g., wires, beam leads) are also provided.

Abstract: A semiconductor device includes: a semiconductor carrier with a top surface on which a plurality of electrodes are disposed; and a semiconductor element electrically connected through a plurality of bump electrodes to the plurality of associated electrodes. The plurality of electrodes are substantially uniformly spaced.

Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: A plurality of vertically spaced-apart microsprings are provided to increase microspring contact force, contact area, contact reliability, and contact yield. The microspring material is deposited, either as a single layer or as a composite of multiple sub layers, to have a tailored stress differential along its cross-section. A lower microspring may be made to push up against an upper microspring to provide increased contact force, or push down against a substrate to ensure release during manufacture. The microsprings may be provided with similar stress differentials or opposite stress differentials to obtain desired microspring profiles and functionality. Microsprings may also be physically connected at their distal ends for increased contact force. The microsprings may be formed of electrically conductive material or coated with electrically conductive material for probe card and similar applications.

Abstract: A semiconductor device which uses a semiconductor element having main current input/output electrodes, one and the other of which are extended up to a one surface and a remaining surface of a semiconductor chip respectively for causing one of the input/output electrodes to be contacted with a conductive layer of a insulating substrate, whereby the semiconductor element is supported on or above the insulating substrate. A conductive strip which is made of a composite material of carbon and aluminum or a composite material of carbon and copper is used for connection between the remaining input/output electrode of the semiconductor chip and the conductive layer of the insulating substrate.

Abstract: One of the aspects of the present invention is to provide a semiconductor module, which includes at least one semiconductor device including a semiconductor element molded with a resin package having a main surface and a side surface, and a plurality of terminals extending from the side surface and being bent towards a direction away from the main surface. It also includes a box-shaped hollow casing including a base member having a plurality of through-holes and an opening opposing to the base member, for receiving the semiconductor device with the terminals of the semiconductor device inserted into the through-holes. Further, the semiconductor module includes an insulating resin member filling up a gap defined between the semiconductor device and the casing so as to cover portions of the terminals at the side surface of the resin package of the semiconductor device.

Abstract: Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g.

Abstract: A semiconductor die featuring vertical rows of bonding pad structures is disclosed. The rows of bonding pad structures are located vertically in the Y direction, or traversing the width of the semiconductor die. A vertical row of bonding pad structures is located on each side of the semiconductor die while a third vertical row of bonding pad structures is located in the center of the semiconductor die. A first set of wire bonds connect each bonding pad structure located on the sides of the semiconductor die to a conductive lead structure located on a ceramic package. A second set of wire bonds connect each bonding pad structure located in the center of the semiconductor die to a lead on chip (LOC) structure located on the semiconductor die.

Abstract: A wafer or a portion of a wafer including capped chips such as surface acoustic wave (SAW) chips is provided with terminals by applying a terminal-bearing element such as a dielectric element with terminals and leads thereon, or a lead frame, so that the terminal-bearing element covers the caps, and the leads are aligned with channels or other depressions between the caps. The leads are connected to contacts on the wafer, and the wafer is severed to form individual units, each including terminals supported by the cap and connected to the contacts by the leads. The resulting units can be handled and processed in the same manner as ordinary chips or chip assemblies.

Abstract: Resilient spring contacts for use in wafer test probing are provided that can be manufactured with a very fine pitch spacing and precisely located on a support substrate. The resilient contact structures are adapted for wire bonding to an electrical circuit on a space transformer substrate. The support substrates with attached spring contacts can be manufactured together in large numbers and diced up and tested before attachment to a space transformer substrate to improve yield. The resilient spring contacts are manufactured using photolithographic techniques to form the contacts on a release layer, before the spring contacts are epoxied to the support substrate and the release layer removed. The support substrate can be transparent to allow alignment of the contacts and testing of optical components beneath. The support substrate can include a ground plane provided beneath the spring contacts for improved impedance matching.

Abstract: A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces include first and second electrode surfaces respectively, and first and second electrically conductive members covering the first and second electrode surfaces respectively as seen in the thickness direction to be electrically connected to the first and second electrode surfaces respectively.

Abstract: In stack packaging, an IC chip in an upper layer and an IC chip in a lower layer are insulated from each other by use of an insulating adhesive and the like. Thus, if an analog IC chip is stacked in the upper layer, a substrate is set in a floating state. Accordingly, there arises a problem that desired characteristics cannot be obtained. A conductive layer is disposed on an IC chip, and an analog IC chip is fixed on the conductive layer. The conductive layer is connected to a fixed potential pattern through a bonding wire and the like. Thus, a fixed potential can be applied to a rear surface (substrate) of the analog IC chip. Consequently, a mounting structure including the analog IC chip stacked in the upper layer can be realized. In addition, versatility of stack packaging for a circuit device including the analog IC chip can be improved, and a mounting area can be reduced. Moreover, characteristics can be improved.

Abstract: A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.

Abstract: An IC package keeping the attachment level of leads on chip during molding process, mainly comprises a plurality of leads of a Lead-On-Chip (LOC) leadframe, a chip adhered under the leads, a plurality of bonding wires electrically connecting the chip to the leads, a plurality of first supporting columns disposed above some of the leads, a plurality of second supporting columns disposed under the some of the leads and a molding compound. The molding compound encapsulates the chip, the bonding wires, inner portions of the leads and sides of the first and second supporting columns. Therein, the first and second supporting columns are longitudinally corresponding to each other and adjacent the chip. The thickness including one of the first supporting columns, a corresponding one of the second supporting columns and one of the leads disposed corresponding to the selected first supporting column and the selected second supporting column is approximately as same as that of the molding compound.