Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature distal from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.

Abstract: According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type silicon layer on one surface and at least one of a PN junction, an electrode film, and a protective film on another surface. The method includes the steps of forming a Si—Ti junction by forming a first electrode film made of titanium on the N-type silicon layer; forming a second electrode film made of Al—Si on the first electrode film; forming a third electrode film made of Ni on the second electrode film; and heating the silicon substrate after forming the third electrode film. A titanium silicide layer is not formed between the N-type silicon layer and the first electrode film.

Abstract: A bump manufacturing method may be provided. The bump manufacturing method may include forming a bump on an electrode pad included in a semiconductor device, and controlling a shape of the bump by reflowing the bump formed on the semiconductor device under an oxygen atmosphere.

Abstract: A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects.

Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.

Abstract: A semiconductor device includes a semiconductor chip, a contact pad of the semiconductor chip and a first layer arranged over the contact pad. The first layer includes niobium, tantalum or an alloy including niobium and tantalum.

Abstract: A semiconductor device of an embodiment includes: a semiconductor layer made of p-type nitride semiconductor; an oxide layer formed on the semiconductor layer, the oxide layer being made of a crystalline nickel oxide, and the oxide layer having a thickness of 3 nm or less; and a metal layer formed on the oxide layer.

Abstract: Embodiments relate to growing an epitaxy gallium-nitride (GaN) layer on a porous silicon (Si) substrate. The porous Si substrate has a larger surface area compared to non-porous Si substrate to distribute and accommodate stress caused by materials deposited on the substrate. An interface adjustment layer (e.g., transition metal silicide layer) is formed on the porous silicon substrate to promote growth of a buffer layer. A buffer layer formed for GaN layer may then be formed on the silicon substrate. A seed-layer for epitaxial growth of GaN layer is then formed on the buffer layer.

Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.

Abstract: An electronic component includes a printed conductor structure on a substrate, as well as a film which contacts the printed conductor structure. The film has a smaller layer thickness than the printed conductor. The printed conductor structure has a region which is covered by the film for the purpose of contacting.

Abstract: The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.

Abstract: A mock bump system includes providing a flip chip integrated circuit having an edge and forming a mock bump near the edge.

Abstract: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Abstract: An interconnect structure located on a semiconductor substrate within a dielectric material positioned atop the semiconductor substrate is provided having an opening within the dielectric material, the opening includes an electrically conductive material extending from the bottom to the top, and contacting the sidewall; a first layer located on the sidewall of the opening, the first layer is made from a material including titanium oxide or titanium silicon oxide; a second layer located between the first layer and the electrically conductive material, the second layer is made from a material selected from the group TiXOb, TiXSiaOb, XOb, and XSiaOb, X is Mn, Al, Sn, In, or Zr; and a third layer located along a top surface of the electrically conductive material, the third layer is made from a material selected from the group TiXOb, TiXSiaOb, XOb, and XSiaOb, X is Mn, Al, Sn, In, or Zr.

Abstract: A conductive bump formed on an electrode surface of an electronic component. This conductive bump is composed of a plurality of photosensitive resin layers having different conductive filler contents. Consequently, this conductive bump is able to realize conflicting functions, namely, improvement in adhesion strength with the electrode and reduction of contact resistance.

Abstract: A metallization layer for a semiconductor device includes a first layer made of Pt and having a thickness greater than or equal to 15 ? and less than or equal to 50 ?, and a second layer formed on the first layer and made of a plurality of metallic sub-layers such as Ti/Pt/Au. A semiconductor device fabricated from the metallization layer includes a semiconductor substrate having a top layer and mesa structure and corresponding surface for securing an insulating layer and a corresponding exposed surface, and wherein the metallization layer is deposited over the insulating layer and exposed surface. Methods for forming the metallization layer are also disclosed.

Abstract: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Abstract: A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.

Abstract: A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom potion. A difference of C content in the top portion and the bottom potion is less than 2 at %. An oxygen content in a surface of the conductor is less than about 1 at %.

Abstract: One exemplary disclosed embodiment comprises a sintered porous metallic film as a die attach mechanically connecting a backside of a semiconductor die to a substrate of a package. Another exemplary disclosed embodiment comprises a sintered porous metallic film as an electrical connection between an electrode on an active surface of a semiconductor die and a substrate of a package. The porous metallic film may be integrated as a prefabricated film or may be created at the wafer or substrate level. By providing a conformal bond through the presence of pores in the metallic film, the sintered connection can provide a reliable mechanical connection with a lower effective elastic modulus. Thermal expansion stresses between die and substrate are thereby accommodated for robustness against thermal cycling, which is of particular relevance for high performance power modules and automotive applications.

Abstract: In one embodiment, a method of forming a semiconductor package includes applying a film layer having through openings over a carrier and attaching a back side of a semiconductor chip to the film layer. The semiconductor chip has contacts on a front side. The method includes using a first common deposition and patterning step to form a conductive material within the openings. The conductive material contacts the contacts of the semiconductor chip. A reconfigured wafer is formed by encapsulating the semiconductor chip, the film layer, and the conductive material in an encapsulant using a second common deposition and patterning step. The reconfigured wafer is singulated to form a plurality of packages.

Abstract: A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure.

Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects.

Abstract: A semiconductor device of an embodiment includes: a semiconductor layer made of p-type nitride semiconductor; an oxide layer formed on the semiconductor layer, the oxide layer being made of a polycrystalline nickel oxide, and the oxide layer having a thickness of 3 nm or less; and a metal layer formed on the oxide layer.

Abstract: According to one embodiment, between the mounting substrate and the semiconductor chip, there is a joint support layer including a metal or its alloy selected from the group of Cu, Al, Ag, Ni, Cr, Zr and Ti and a melt layer laminated across the joint support layer, and formed of a metal selected from the group of Sn, Zn and In or of an alloy of at least two metals selected from the same metals. The process of joining the mounting substrate and the semiconductor chip includes intervening a joining layer which is formed, at least for its outermost layer, by the melt layer, maintaining the temperature to be higher than the melting point of the melt layer, then forming an alloy layer which has a higher melting point than the melt layer by liquid phase diffusion.

Abstract: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Abstract: The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.

Abstract: Method of protecting a liner in a previously formed deep trench module from subsequent processing steps, and resulting structure. A deep trench module includes a deep trench with one or more liner films and a fill material in an SOI substrate. A mask layer is patterned to form first and second masks aligned over the liner films on first and second sidewalls of the deep trench, respectively. Further etching creates a polysilicon tab under the first mask which protects the liner film adjacent the first sidewall from being exposed during subsequent etches. The second mask protects its underlying polysilicon from subsequent etches to maintain a conduction strap from SOI layer to deep trench. The masks are removed. An isolation film is deposited on the substrate and planarized to form and isolation region. The resulting structure has a polysilicon tab interposed between the deep trench liner and the isolation region.

Abstract: A paste for forming an interconnect includes a mixture of binder particles, filler particles and flux material, binder particles having a melting temperature that is lower than that of the filler particles, and the proportion of the binder particles and the filler particles being selected such when heat is applied to melt the binder particles the shape of the paste as deposited is substantially retained thereby allowing for the paste to be used for forming interconnect structures.

Abstract: An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.

Abstract: Providing the conductive paste for the material forming the conductive connecting member without disproportionately located holes (gaps), coarse voids, and cracks, which improves thermal cycle and is excellent in crack resistance and bonding strength.

Abstract: The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting nanorods from carbon nanotubes suspended in an aqueous solution. The assembled nanorods are suitable for use as nanoscale interconnects in CMOS-based devices and sensors. Metallic nanoparticles or carbon nanotubes are assembled into lithographically patterned vias by applying an external electric field. Since the dimensions of nanorods are controlled by the dimensions of vias, the nanorod dimensions can be scaled down to the low nanometer range. The aqueous assembly process is environmentally friendly and can be used to make nanorods using different types of metallic particles as well as semiconducting and metallic nanaotubes.

Abstract: An anode for an organic light emitting device which introduces a metal oxide to improve flows of charges, and an organic light emitting device using the anode. The anode for the organic light emitting device has excellent charge injection characteristics, thereby improving power consumption of the organic light emitting device.

Abstract: A semiconductor device according to an embodiment includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate, and a semiconductor element mounted on the wiring layer. In this semiconductor device, the wiring layer includes a first copper-containing material containing copper and a metal having the thermal expansion coefficient smaller than that of copper and the thermal expansion coefficient of the first copper-containing material is smaller than that of copper.

Abstract: Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 ?m; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 ?m from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 ?m from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.

Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.

Abstract: An IC die includes active circuitry and I/O nodes tied together in first net and at least a second net. A first die pad and a second die pad adjacent thereto are coupled to the first and second net, respectively. A redirect layer (RDL) coupled to the die pads over a first dielectric vias includes a first RDL trace lateral coupling the first die pad and first RDL pad and a second RDL trace coupling the second die pad and second RDL pad. The first RDL pad includes an RDL notch facing the second RDL trace. Under bump metallization (UBM) pads on a second dielectric include a first UBM pad coupled to the first RDL pad over a second dielectric via. A first metal bonding connector is on the first UBM pad. The first UBM pad or first metal bonding connector overhangs the first RDL pad over the notch.

Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.

Abstract: Method for formation of at least one electrical conductor on a semiconductor material (1), characterized in that it comprises the following steps: (E1)—deposition by serigraphy of a first high-temperature paste; (E2)—deposition by serigraphy of a second low-temperature paste at least partially superposed onto the first high-temperature paste deposited during the preceding step.

Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.

Abstract: A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.

Abstract: Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature to cause the self-formation of a MnSiOx barrier layer.

Abstract: A transparent conductive film includes indium oxide containing hydrogen and cerium and having a substantially polycrystalline structure, in which specific resistance of the transparent conductive film is no greater than 3.4×10?4?·cm and the carrier mobility is no less than 70 cm2/Vs.

Abstract: A process for making an integrated circuit, a wafer level integrated circuit package or an embedded wafer level package includes forming copper contact pads on a substrate or substructure. The substructure may include devices and the contact pads may be used for forming electrical couplings to the devices. For example, copper plating may be applied to a substructure and the copper plating etched to form copper contact pads on the substructure. An etching process may be applied to remove barrier layer material on the substructure, such as adjacent to the copper pads. For example, a hydrogen peroxide etch may be applied to remove titanium-tungsten from a surface of the substructure. The pads are again etched to remove barrier layer etchant, byproducts and/or oxide from the pads. Contamination control steps may be performed, such as quick-dump-and-rinse (QDR) and spin-rinse-and-dry (SRD) processing.

Abstract: When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.

Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.