Consisting Of Layered Constructions Comprising Conductive Layers And Insulating Layers, E.g., Planar Contacts (epo) Patents (Class 257/E23.019)
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Patent number: 7750468Abstract: A semiconductor device includes: a semiconductor substrate that has an integrated circuit, a passivation film formed above the integrated circuit, and an electrode electrically connected to the integrated circuit, the passivation film having an uneven surface, the electrode having at least a portion exposed through the passivation film; a first resin layer that is disposed on the passivation film; a second resin layer that covers the passivation film and the first resin layer; and a wiring that extends from the electrode to a first part of the second resin layer above the first resin layer, the electrode passing on a second part of the second resin layer above the passivation film.Type: GrantFiled: February 18, 2008Date of Patent: July 6, 2010Assignee: Seiko Epson CorporationInventor: Tatsuhiko Asakawa
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Patent number: 7745325Abstract: A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.Type: GrantFiled: May 16, 2007Date of Patent: June 29, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ho Koh, Byung-Hong Chung, Won-Jin Kim, Hyun Park, Ji-Young Min
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Patent number: 7737536Abstract: Structures, in various embodiments, are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. In an embodiment, a transmission line is disposed on a first layer of insulating material, where the first layer of insulating has a thickness equal to or less than 1.0 micrometer. The transmission line may be structured with a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is disposed on the transmission line.Type: GrantFiled: July 18, 2006Date of Patent: June 15, 2010Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7737554Abstract: An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 layer have widths of greater than about a minimum feature size; and vias connecting the first and the second M1 layers.Type: GrantFiled: June 25, 2007Date of Patent: June 15, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jeffrey Junhao Xu
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Publication number: 20100140806Abstract: A method for forming a super contact in a semiconductor device is disclosed. The method enables forming a barrier film selectively on the silicon substrate, leaving the metal contact exposed for perfect isolation of the metal pad from the silicon substrate after formation of the super contact.Type: ApplicationFiled: December 1, 2009Publication date: June 10, 2010Inventor: Sang Chul KIM
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Publication number: 20100140779Abstract: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) structure is formed over the temporary carrier. The IPD structure includes an inductor, resistor, and capacitor. Conductive posts are mounted to the IPD structure, and first semiconductor die is mounted to the IPD structure. A wafer molding compound is deposited over the conductive posts and the first semiconductor die. A core structure is mounted to the conductive posts over the first semiconductor die. The core structure includes a semiconductor material. Conductive through silicon vias (TSVs) are formed in the core structure. A redistribution layer (RDL) is formed over the core structure. A second semiconductor die is mounted over the semiconductor device. The second semiconductor die is electrically connected to the core structure.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
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Patent number: 7732923Abstract: An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.Type: GrantFiled: January 20, 2005Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhen-Cheng Wu, Yung-Cheng Lu, Chung-Chi Ko
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Patent number: 7732935Abstract: A wiring board includes a substrate made of an insulation material and wired by a conductive material. A plurality of electrodes is formed on a surface of the substrate. A non-Au electrode not having an Au surface layer and an Au electrode having the Au surface layer are formed as the electrodes.Type: GrantFiled: April 20, 2006Date of Patent: June 8, 2010Assignees: Ricoh Company, Ltd., Ricoh Microelectronics Co., Ltd.Inventor: Eiji Moriyama
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Patent number: 7728435Abstract: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.Type: GrantFiled: June 20, 2008Date of Patent: June 1, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Sakuma, Yasuhiko Matsunaga, Fumitaka Arai, Kikuko Sugimae
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Patent number: 7728444Abstract: A difference in delay of signal transmission due to the wiring within a board is minimized. A wiring board includes wiring for connecting terminals included in one of a plurality of semiconductor chips to terminals included in another one of the plurality of semiconductor chips, through branch points. Each of the plurality of semiconductor chips includes first and second terminals. Moreover, a first wiring up to the first terminals and a second wiring up to the second terminals are in a positional relationship of being shifted parallel to each other in a planar direction of the wiring board so as not to come into electrical contact with each other.Type: GrantFiled: January 9, 2008Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventor: Akimori Hayashi
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Publication number: 20100127400Abstract: A semiconductor module is disclosed, including a substrate and at least one semiconductor component in bottom contact with the substrate. The semiconductor component including a main current branch sandwiched between the bottom and top of the semiconductor component. The side edges of a barrier layer zone coincide with the side edge portions of the semiconductor component between the top and the bottom. The space above the substrate and to the side of the semiconductor component is packed with an insulating compound at least up to the level of the top of the semiconductor component. Topping the semiconductor component and parallel thereto is a patterned or unpatterned metallization connected to a contact pad on the top of the semiconductor component.Type: ApplicationFiled: November 19, 2009Publication date: May 27, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Peter Kanschat, Indrajit Paul
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Patent number: 7714426Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.Type: GrantFiled: July 7, 2007Date of Patent: May 11, 2010Inventors: Keith Gann, W. Eric Boyd
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Patent number: 7714443Abstract: An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.Type: GrantFiled: July 19, 2006Date of Patent: May 11, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei Chen, Anbiarshy Wu, Shih-Hsun Hsu, Shang-Yun Hou, Hsueh-Chung Chen, Shin-Puu Jeng
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Publication number: 20100109135Abstract: A semiconductor die package, and methods of making the same. The package includes a leadframe and a clip structure. The clip structure is formed, such that a portion of the clip structure points towards the semiconductor die and is coplanar with the leadframe. The semiconductor die package further includes a housing material covering at least a portion of the leadframe, the semiconductor die, and the clip structure. The housing material has an external recess that holds a portion of the clip structure.Type: ApplicationFiled: November 6, 2008Publication date: May 6, 2010Inventor: Armand Vincent C. Jereza
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Patent number: 7709401Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.Type: GrantFiled: February 22, 2008Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Fen Chen, Cathryn Jeanne Christiansen, Michael Anthony Shinosky, Timothy Dooling Sullivan
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Patent number: 7701057Abstract: A semiconductor device having structures for reducing substrate noise coupled from through die vias (TDVs) is described. In one example, a semiconductor device has a substrate, at least one signal through die via (TDV), and ground TDVs. The substrate includes conductive interconnect formed on an active side thereof. The conductive interconnect includes ground conductors and digital signal conductors. Each signal TDV is formed in the substrate and is electrically coupled to at least one of the digital signal conductors. The ground TDVs are formed in the substrate in a ring around the at least one signal TDV. The ground TDVs are electrically coupled to the ground conductors. The ground TDVs provide a sink for noise coupled into the substrate from the signal TDVs. In this manner, the ground TDVs mitigate noise coupled to noise-sensitive components formed on the substrate.Type: GrantFiled: April 25, 2007Date of Patent: April 20, 2010Assignee: XILINX, Inc.Inventors: Arifur Rahman, Stephen M. Trimberger
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Publication number: 20100078792Abstract: A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.Type: ApplicationFiled: December 4, 2009Publication date: April 1, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: David J. Corisis, Jerry M. Brooks, Matt E. Schwab, Tracy V. Reynolds
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Publication number: 20100078799Abstract: A method of forming a microelectronic package is provided. The method includes providing a silicon substrate having a plurality of carbon nanotubes disposed on a silicon layer and coupling the silicon substrate to a top surface of a packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of substrate pads of the packaging substrate. The method also includes removing the silicon substrate from the packaging substrate and disposing a die adjacent to the top surface of the packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of bump pads of the die.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Edward A. Zarbock, Gloria Alejandra Camacho Bragado
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Patent number: 7687877Abstract: An interconnect structure is provided that includes a dielectric material 52? having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52? has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52? and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58.Type: GrantFiled: May 6, 2008Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, David V. Horak, Takeshi Nogami, Shom Ponoth
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Patent number: 7679192Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film formed over the substrate, a trench formed in the interlayer insulating film, a cover film formed over the inside surface of the trench, a barrier layer formed over the cover film; and a metal line formed over the barrier layer which fills and seals the trench. The metal line is in direct contact with the semiconductor substrate.Type: GrantFiled: December 28, 2006Date of Patent: March 16, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Han-Choon Lee
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Publication number: 20100059876Abstract: There is provided an electronic component package. The electronic component package includes: a core layer including a plurality of insulating layers formed by impregnating a base material with a resin, wherein a hollow portion is formed in the core layer; core wiring layers each disposed between the insulating layers; and an electronic component disposed in the hollow portion. The electronic component and the core wiring layer are electrically connected to each other by a bonding wire.Type: ApplicationFiled: September 5, 2008Publication date: March 11, 2010Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Hiroshi Shimizu, Hiroyuki Kato, Takahiro Takenouchi
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Publication number: 20100052189Abstract: Electronic component mounting structure (1) comprising electronic component (10) provided with a plurality of electrode terminals (10a), mounting substrate (12) provided with connector terminals (12a) in positions corresponding to electrode terminals (10a), wherein electrode terminal (10a) is connected to connector terminal (12a) via protrusion electrode (13) disposed on electrode terminal (10a) or connector terminal (12a), and protrusion electrode (13) includes at least conductive filler (13a) and photosensitive resin (13b), and varies in resin component crosslink density of photosensitive resin (13b) in the height direction of protrusion electrode (13).Type: ApplicationFiled: November 20, 2007Publication date: March 4, 2010Inventors: Daisuke Sakurai, Yoshihiko Yagi
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Patent number: 7671382Abstract: A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.Type: GrantFiled: August 3, 2006Date of Patent: March 2, 2010Assignee: Mitsubishi Electric CorporationInventors: Shingo Sudo, Tatsuo Ota, Nobutake Taniguchi, Hiroshi Yoshida, Hironori Kashimoto
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Patent number: 7670902Abstract: A method for fabricating an integrated circuit device. A plurality of MOS transistor devices are formed overlying a semiconductor substrate. Each of the MOS transistor devices includes a nitride cap and nitride sidewall spacers. An interlayer dielectric layer is formed overlying the plurality of MOS transistor devices. A portion of the interlayer dielectric material is removed to expose at least portions of three MOS transistor devices and expose at least three regions between respective MOS transistor devices. The method deposits polysilicon fill material overlying the exposed three regions and overlying the three MOS transistor devices. The method performs a chemical mechanical planarization process on the polysilicon material to reduce a thickness of the polysilicon material exposing a portion of the interlayer dielectric material until the cap nitride layer on each of the MOS transistors has been exposed using the cap nitride layer as a polish stop layer.Type: GrantFiled: July 26, 2005Date of Patent: March 2, 2010Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Chris C. Yu, Hongxiu Peng
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Patent number: 7667318Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.Type: GrantFiled: October 22, 2008Date of Patent: February 23, 2010Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
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Publication number: 20100038802Abstract: A method of stacking wafers includes: providing a first wafer including a first metal connection layer; forming a first passivation layer over the first metal connection layer; forming a first bondpad in the first passivation layer to form a first bondpad layer; providing a second wafer including second metal connection layer; forming a second passivation layer over the second metal connection layer; forming a second bondpad in the second passivation layer to form a second bondpad layer; forming at least one of a first conductive adhesive layer over the first bondpad layer and a second conductive adhesive layer over the second bondpad layer; and stacking the second wafer on the first wafer by bonding respective faces of the second bondpad layer with the first bondpad layer via the at least one of the first conductive adhesive layer and the second conductive adhesive layer.Type: ApplicationFiled: January 5, 2009Publication date: February 18, 2010Inventors: Min-Liang CHEN, Hai-Jun Zhao
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Publication number: 20100032848Abstract: It is described a bond pad structure and a method for producing the same, the bond pad structure (1), comprising: a substrate (3) having a surface (17) to be electrically contacted; a first isolator layer (5) contacting the surface (17) of the substrate in a first region (a); a first metal layer (9) contacting the surface (17) of the substrate (3) in a second region (b) adjacent the first region (a) and partly overlapping the first isolator layer (5); a second isolator layer (11) at least partly overlapping the first isolator layer (5) and the first metal layer (9); a second metal layer (13) at least partly overlapping the second isolator layer (11) in the second region (b); wherein a maximum thickness (U) of the second metal layer (13) perpendicular to the surface (17) of the substrate (3) is smaller than a maximum thickness (t0) of the first isolator layer (5) perpendicular to the surface (17) of the substrate (3).Type: ApplicationFiled: November 12, 2007Publication date: February 11, 2010Applicant: NXP, B.V.Inventors: Bengt Philippsen, Hans-Joerg Klammer
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Publication number: 20100032816Abstract: This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil.Type: ApplicationFiled: August 5, 2008Publication date: February 11, 2010Applicant: Infineon Technologies AGInventors: Joachim MAHLER, Ralf WOMBACHER, Ralf OTREMBA
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Patent number: 7659627Abstract: A photodiode balanced in increased sensitivity and speed. The photodiode includes a semiconductor substrate, an active region formed on the semiconductor substrate, and a comb electrode connected to the active region. The comb electrode includes a plurality of electrode fingers, and each of the electrode fingers includes a transparent electrode contacting the active region, and an opaque electrode formed on the transparent electrode. Here, the width of the opaque electrode is set smaller than the width of the transparent electrode.Type: GrantFiled: December 5, 2007Date of Patent: February 9, 2010Assignees: FUJIFILM Corporation, Massachusetts Instutite of TechnologyInventors: Yukiya Miyachi, Wojciech P. Giziewicz, Jurgen Michel, Lionel C. Kimerling
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Publication number: 20100019383Abstract: In this manufacturing method of a semiconductor device, a metal plate having a plurality of projection electrodes in each of a plurality of semiconductor device formation areas is prepared. Next, the projection electrodes of each of the semiconductor formation areas are aligned corresponding to external connection electrodes of each semiconductor construction, and each semiconductor construction is separately arranged on the projection electrodes in the semiconductor device formation areas. Next, an insulating layer formation sheet is arranged on the metal plate, and the metal plate and the insulating layer formation sheet are joined by heat pressing. Then, the metal plate is patterned and a plurality of upper layer wirings that connect to the projection electrodes is formed.Type: ApplicationFiled: July 21, 2009Publication date: January 28, 2010Applicant: CASIO COMPUTER CO., LTD.Inventors: Ichiro MIHARA, Takeshi Wakabayashi
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Patent number: 7652363Abstract: Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored in the semiconductor chip, the integrated circuit does not operate and it is impossible to analyze the information. Further, there is provided a processing detector circuit for detecting that the wiring lines have been tampered with. When the processing detector circuit detects a change in the state of the wiring lines, the integrated circuit is reset. Thus, it is possible to improve the security of information stored on the card.Type: GrantFiled: May 24, 2006Date of Patent: January 26, 2010Assignee: Renesas Technology Corp.Inventors: Hirotaka Mizuno, Yoshio Masumura, Takeo Kon, Yukio Kawashima
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Publication number: 20100013087Abstract: An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric layers has openings with metalization underneath coupled to at least one of the metal conductors, and solder bumps protruding from each of the openings.Type: ApplicationFiled: July 17, 2008Publication date: January 21, 2010Inventor: Luke England
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Patent number: 7646098Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.Type: GrantFiled: April 10, 2008Date of Patent: January 12, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
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Patent number: 7642651Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.Type: GrantFiled: November 16, 2006Date of Patent: January 5, 2010Assignee: Micron Technology, Inc.Inventors: Todd Albertson, Darin Miller, Mark Anderson
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Patent number: 7633164Abstract: The present invention includes a liquid crystal display device having an oxide film having high adhesiveness to a substrate to thereby prevent oxidation of a wiring material or the like, and includes, an electrode or a terminal electrode having high conductivity, and a manufacturing method therefor. Consequently, in the present invention, a liquid crystal display device has an electrode terminal of a TFT substrate, wherein the electrode is formed on an insulator and is comprised of a conductive layer mainly consisting of copper and an oxide covering an outer part, further the oxide is a layered structure of transparent electrodes, the layered portion having ohmic contact, and the oxide mainly consists of manganese oxide.Type: GrantFiled: April 10, 2007Date of Patent: December 15, 2009Assignees: Tohoku University, Advanced Interconnect Materials LLCInventors: Junichi Koike, Hideaki Kawakami
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Publication number: 20090302453Abstract: A method for manufacturing a silicon chip package for a circuit board assembly provides a package with a silicon chip and an array of first contact pads that are provided by a first conductive material. A plurality of second contact pads are provided from a gold material having a hardness different than that of the first contact pads. The second contact pads are soldered to the first contact pads of the package. A circuit board assembly is assembled by providing a circuit board substrate with at least one socket with contact pads. The second contact pads of the package are assembled to the circuit board substrate contact pads.Type: ApplicationFiled: June 4, 2008Publication date: December 10, 2009Applicant: SUN MICROSYSTEMS, INC.Inventor: Ashur S. Bet-Shliemoun
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Patent number: 7626255Abstract: Provided is a device, an assembly comprising said device, a sub-assembly and an element suitable for use in the assembly. The device comprises a body of an electrically insulating material having a first side and an opposite second side, the body being provided with conductors according to a desired pattern, said conductors being anchored in the body. The body is provided with a through-hole extending from the first side to the second side of the body and having a surfacial area which is smaller on the first side than on the second side. Such a device can very suitably be used in an assembly comprising an element which is a sensor, preferably a chemical sensor, and particularly a biosensor.Type: GrantFiled: October 14, 2004Date of Patent: December 1, 2009Assignee: Koninklijke Philips Electronics N.V.Inventors: Johannus Wilhelmus Weekamp, Menno Willem Jose Prins
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Patent number: 7598615Abstract: In an analytic structure for failure analysis of a semiconductor device, a plurality of analytic regions are arranged in regions of a semiconductor substrate. A plurality of semiconductor transistors having an array structure are arranged in each of the analytic regions. A plurality of interconnection structures connect the semiconductor transistors, each comprising multiple layered metal patterns and multiple layered plugs interposed between the multiple layered metal patterns. A first number of layers of the multiple layered metal patterns and multiple layered plugs is different in one of the analytic regions than a second number of layers of the multiple layered metal patterns and multiple layered plugs in another one of the analytic regions.Type: GrantFiled: February 3, 2006Date of Patent: October 6, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Am Lee, Jong-Hyun Lee
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Publication number: 20090243107Abstract: At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows a Micro-Electro-Mechanical Systems device or semiconductor to be subjected to temperatures above 385° C. without risking gold diffusion. Removing the risk of gold diffusion allows further elevated temperature processing. Bonding a device substrate to a carrier substrate can be an elevated temperature process.Type: ApplicationFiled: March 26, 2008Publication date: October 1, 2009Inventor: Richard A. Davis
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Publication number: 20090236749Abstract: One aspect is a method including providing a carrier having a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer; attaching at least two semiconductor chips to the carrier; applying a second insulating layer over the carrier; opening the second insulating layer until the carrier is exposed; depositing a metal layer over the opened second insulating layer; and separating the at least two semiconductor chips after depositing the metal layer.Type: ApplicationFiled: March 18, 2008Publication date: September 24, 2009Applicant: Infineon Technologies AGInventors: Ralf Otremba, Henrik Ewe, Klaus Schiess, Manfred Mengel
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Patent number: 7592244Abstract: A method of manufacturing a semiconductor device includes the step of forming a first insulating section with a protruding section on a semiconductor substrate, the step of forming a first conducting section on the first insulating section so as to pass on a surface of the protruding section, the step of forming a second insulating section for partially covering the first conducting section above the first insulating section so as to expose at least a part of the first conducting section formed on the surface of the protruding section, and the step of forming, on the second insulating section, a second conducting section electrically connected to the first conducting section via an exposed section of the first conducting section exposed from the second insulating section.Type: GrantFiled: April 3, 2006Date of Patent: September 22, 2009Assignee: Seiko Epson CorporationInventor: Yasunori Kurosawa
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Publication number: 20090224385Abstract: A package structure of an integrated circuit device comprises a copper foil substrate, an integrated circuit device, a plurality of metal wires and an encapsulation material. The copper foil substrate comprises an IC bonding area, a plurality of conductive areas and an insulating dielectric material. The integrated circuit device is mounted on the surface of the IC bonding area, and is electrically connected to the plurality of conductive areas through the metal wires. The insulating dielectric material is between the IC bonding area and the conductive areas, and is also between two adjacent conductive areas. In addition, the encapsulation material covers the IC bonding area, the conductive areas and the integrated circuit device.Type: ApplicationFiled: March 3, 2009Publication date: September 10, 2009Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY INC.Inventors: SHIH HSIUNG CHAN, SHEN BO LIN, PIN CHUAN CHEN
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Patent number: 7582909Abstract: An assembly and adhesive layer for semiconductor components is arranged between a silicon support (submount) and an electronic functional element for the formation of an electrically-conducting connection between the silicon support and the functional element. The assembly and adhesive layer are arranged on the support. The assembly and adhesive layer are made from a Ti/TiN layer (6), applied to an aluminum contact surface (5) of the silicon support (1), by means of a deposition method. The aluminum contact surface (5) is located on a landing pad (2) on the silicon support (1).Type: GrantFiled: June 9, 2006Date of Patent: September 1, 2009Assignee: Infineon Technologies AGInventors: Melanie Ring, Benjamin Prodinger, Werner Kuhlmann
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Patent number: 7576424Abstract: A semiconductor device including: a semiconductor substrate on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the semiconductor substrate, arranged along a straight line, and extending in a direction which intersects the straight line; and a plurality of electrical connection sections formed on the resin protrusions and electrically connected to the electrodes.Type: GrantFiled: August 2, 2006Date of Patent: August 18, 2009Assignee: Seiko Epson CorporationInventor: Shuichi Tanaka
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Publication number: 20090194863Abstract: A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at the front side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole; and a second outer insulator layer disposed at the rear side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole which exposes a portion of the internal wiring.Type: ApplicationFiled: January 21, 2009Publication date: August 6, 2009Inventor: Yu-Nung Shen
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Publication number: 20090194866Abstract: An insulating film covering the upper surface of an external connection electrode of a semiconductor construct is formed. A mask metal layer in which there is formed an opening having a planar size smaller than that of the external connection electrode is formed on the insulating film. The mask metal layer is used as a mask to apply a laser beam to the insulating film, such that a connection opening reaching the external connection electrode is formed in the insulating film. A wiring line is formed on the insulating film in such a manner as to be connected to the external connection electrode via the connection opening.Type: ApplicationFiled: January 26, 2009Publication date: August 6, 2009Applicant: Casio Computer Co., Ltd.Inventor: Hiroyasu JOBETTO
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Patent number: 7569877Abstract: A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionally, the system includes a plurality of address lines. Each of the plurality of address lines includes a gate region and an inactive region and intersects the plurality of semiconductor wires at a plurality of intersections. The plurality of intersections includes a first intersection and second intersection. The first intersection is associated with the gate region, and the second intersection is associated with the inactive region.Type: GrantFiled: February 24, 2006Date of Patent: August 4, 2009Assignee: California Institute of TechnologyInventors: James R. Heath, Yi Luo, Rob Beckman
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Patent number: 7566972Abstract: A semiconductor device, comprises: a wiring formed on a first insulating film, a second insulating film formed on the first insulating film and on the wiring, a contact hole formed in the second insulating film and located on the wiring, a coating that covers a sidewall of the contact hole and is formed by sputtering the wiring at the bottom of the contact hole, a barrier film formed on the coating and at the bottom of the contact hole, and an electrical conductor deposited in the contact hole.Type: GrantFiled: June 26, 2006Date of Patent: July 28, 2009Assignee: Seiko Epson CorporationInventor: Hiroshi Okamura
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Patent number: RE40887Abstract: A new method is provided for the creation of Input/Output connection points to a semiconductor device package. An extension is applied to the conventional I/O connect points of a semiconductor device, allowing the original I/O point location to be relocated to a new point of I/O interconnect that may be in the vicinity of the original point of I/O interconnect but can also be located at a distance from this original point of I/O interconnect. Layers of passivation and polyimide are provided for proper creation and protection of the extended and relocated I/O pads. Wire bonding is used to further interconnect the relocated I/O pads.Type: GrantFiled: July 15, 2005Date of Patent: September 1, 2009Assignees: Megica Corporation, Etron Technology, Inc.Inventors: Mou-Shiung Lin, Tah-Kang Joseph Ting
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Patent number: RE41355Abstract: The present invention provides a bonding pad structure for integrated circuit devices which allows the active circuits to be placed under bonding pads of the device without affecting the performance of the active circuits. The bonding pad structure is composed of at least two metal layers overlying the active circuits so that the bonding pad may be subjected to thermal and mechanical stresses without damaging the underlying active circuits. The metal layer underlying the bonding pad is patterned and etched forming an array of openings in the metal that may take any shape, e.g. slots, grid, circles. The present invention enables a reduction in the chip area and eliminates the parasitic resistance due to long interconnection wires between bonding pads and active regions.Type: GrantFiled: May 5, 2006Date of Patent: May 25, 2010Assignee: Intel CorporationInventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang