Abstract: A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Abstract: A method of manufacturing a lead frame, includes forming a rectangular first dimple includes, first inclined side surfaces inclined to a depth direction, and arranged in two opposing sides in one direction, and standing side surfaces standing upright to a depth direction, and arranged in two opposing sides in other direction, on a backside of a die pad by a first stamping, and forming a second dimple having second inclined side surfaces inclined on the backside of the die pad by a second stamping, such that a second inclined side surfaces of the second dimple are arranged in side areas of the standing side surfaces of the first dimple, wherein the standing side surfaces are transformed into reversed inclined side surfaces inclined to a reversed direction to the first inclined side surfaces, and a front side of the die pad is semiconductor element mounting surface.

Abstract: An LED package with an extended top electrode and an extended bottom electrode is formed from a first metal and a second metal. An LED is on an inner end of the first metal. An outer end of the first metal has been bent upward twice 90 degrees to form a top flat as an extended top electrode of the package. An outer end of the second metal has been bent downward twice 90 degrees to form a bottom flat as an extended bottom electrode of the package. The LED and a bonding wire may be encapsulated with glue.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.

Abstract: An electronic component including an electronic element, an electrode that is formed on a first surface of the electronic element, a first resin layer that is formed over the first surface of the electronic element, a wiring that is electrically connected to the electrode, a first portion of the wiring extending over the first resin layer, a second resin layer that is formed over the first resin layer and the wiring, the second resin layer having an opening, the opening overlapping the first portion of the wiring, an external terminal that is provided above the second resin layer, the external terminal being connected to the first portion of the wiring via the opening, and a third resin layer that is formed over the second resin layer, the third resin layer being provided around the external terminal.

Abstract: A clip for a semiconductor device package may include a metal sheet including an array of windows and one or more conductive fingers. Each of the conductive fingers has a first end and a second end. The first end is electrically connected to the metal sheet at one of the windows. Each of the conductive fingers is adapted to provide electrical connection to a top semiconductor region of a semiconductor device or a lead frame at the second end.

Abstract: A packaged microchip has a lead frame with a die directly contacting at least a single, contiguous portion of the lead frame. The portion of the lead frame has a top surface forming a concavity and contacting the die. The packaged microchip also has mold material substantially encapsulating part of the top surface of the portion of the lead frame.

Abstract: An LED package with an extended top electrode and an extended bottom electrode is made from a single metal sheet, one manufacturing process embodiment includes: preparing a piece of single metal sheet, forming a first metal and a coplanar second metal, mounting an LED on an inner end of the first metal, wire-bonding top electrode to an inner end of the second metal, encapsulating at least the LED and the bonding wire with a protection glue, bending an outer end of the first metal upward twice 90 degrees to form a top flat as an extended top electrode of the package, and bending an outer end of the second metal downward twice 90 degrees to form a bottom flat as an extended bottom electrode of the package.

Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: A leadframe for the assembly of a semiconductor chip has regions (112) with an original smooth surface of glossy appearance and regions (113, 114, 210) of a frosty appearance with rough surface contours. The regions of rough surface contours include two-dimensional arrays of spots (401) comprising a central area (402) below the original surface (400) and a piled ring (403) above the original surface. The piled ring (403) consists of the leadframe material in amorphous configuration.

Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.

Abstract: A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

Abstract: A system is provided for an integrated circuit package including a leadframe with a lead finger. A groove is in a lead finger for a conductive bonding agent and a passive device is in the groove to be held by the conductive bonding agent.

Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead body and a lead tip, forming a lead protrusion in the lead tip, connecting a device and the external interconnect, and encapsulating the device and the external interconnect.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over another. Conductive pathways that extend around at least one side of at least one of the semiconductor devices provide electrical communication between conductive elements of the semiconductor devices, and optionally, a substrate. The conductive pathways may include self-supporting conductive leads or conductive traces carried by a substrate. Methods for forming semiconductor device assemblies having more than one semiconductor device include bending or wrapping at least one conductive pathway around a side of at least one semiconductor device and providing electrical communication between semiconductor devices of the assembly through the conductive pathways.

Abstract: A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.

Abstract: An integrated circuit package system and method of manufacture therefor includes providing a substrate with a beveled cavity, attaching a down-set conductive die pad with tapered sidewalls for matching with the beveled cavity in the substrate and having the down-set below a lower surface of the substrate, and attaching an integrated circuit over the down-set conductive die pad and electrically connected thereto.

Abstract: The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer.

Abstract: A semiconductor package includes a semiconductor device having a first main surface and a second main surface, a first electrode plate provided on the first main surface, a second electrode plate provided on the second main surface, and a wiring substrate provided between the semiconductor device and the first electrode plate, in which a plurality of opening portions in the side surface of a protruding portion provided on the first electrode plate are engaged respectively with a plurality of engaging portions which face the opening portions and which are provided on the inner side surface of an intrusion opening portion in the wiring substrate into which the protruding portion is intruded.

Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.

Abstract: A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus.

Abstract: An integrated circuit package is described that includes two dice. The active surface of each die includes a plurality of I/O pads. The active surface of the first die is positioned adjacent first surfaces of the leads of a lead frame such that I/O pads from the first die are arranged adjacent corresponding solder pad surfaces on the first surfaces. Similarly, the active surface of the second die is positioned adjacent second surfaces of the leads opposite the first surfaces such that I/O pads from the second die are arranged adjacent corresponding solder pad surfaces on the second surfaces. A plurality of solder joints are arranged to physically and electrically connect I/O pads from the first or second die to associated adjacent solder pad surfaces on the leads. In this way, a single lead frame can be utilized to package two dice, one on either side of the leads of the leadframe.

Abstract: A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die-bonding plane under the chip is desirably prevented.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: A packaged microchip has a lead frame with a die directly contacting at least a single, contiguous portion of the lead frame. The portion of the lead frame has a top surface forming a concavity and contacting the die. The packaged microchip also has mold material substantially encapsulating part of the top surface of the portion of the lead frame.

Abstract: An integrated circuit package system is provided including forming a D-ring comprising half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.

Abstract: A lead frame and a semiconductor device having a lead frame are disclosed. The lead frame is provided with a mount bed to mount a semiconductor chip, first and second lead terminals and first and second extension portions of band-shapes. The first and the second extension portions extend from sides of the first and second lead terminals and are bent. An electronic component is attached to Tip portions of the first and the second extension portions with connection conductors interposed in between.

Abstract: A magnetic sensor is constituted using magnetic sensor chips mounted on stages supported by interconnecting members and a frame having leads in a lead frame. Herein, the stages are inclined upon plastic deformation of the interconnecting members. When the frame is held in a metal mold and the stages are pressed, the interconnecting members are elastically deformed, so that the magnetic sensor chips are bonded onto the stages placed substantially in the same plane and are then wired with the leads. Thereafter, the stages are released from pressure, so that the interconnecting members are restored from the elastically deformed states thereof. When the magnetic sensor chips are combined together to realize three sensing directions, it is possible to accurately measure three-dimensional bearings of magnetism, and the magnetic sensor can be reduced in dimensions and manufactured with a reduced cost therefore.

Abstract: An element includes a hollow space for a mechanically sensitive electrical element. The element includes a first housing part and a second housing part rigidly connected to the first housing part via joint surfaces. The element also includes connection surfaces on a base of a recess in the first housing the first housing part being covered by the second housing part to form an enclosed hollow space.

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip, a solder ball for external connection, wiring for electrically connecting the semiconductor chip and the solder ball, a stress relieving layer provided on the semiconductor chip, and a stress transmission portion for transmitting stress from the solder ball to the stress relieving layer in a peripheral position of an electrical connection portion of the solder ball and wiring.

Abstract: A light emitting device has a cup portion with a bottom surface opening, and one electrode of a light emitting element is connected to the cup portion. The other electrode of the light emitting element is connected to a lead set up from an inner space to outside the cup portion using the opening of the cup portion. Each electrode and lead of the light emitting device can be electrically connected without bonding wires. This prevents shadows or light unevenness from reflecting the shape of the bonding wire, thereby enhancing light-emission efficiency. As an alternative to setting up the lead from inside to the outside of the cup portion, the lead existing outside the cup portion and the other electrode are electrically connected via the bonding wire through the cup portion's opening. Thus, light outputted outside of the light emitting device is not intercepted by the bonding wire.

Abstract: The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each of the mounting portions are electrically connected, a corner portion which connects the plurality of mounting portions and which has a hanging lead piece that supports the mounting portions and an electrode connection piece that connects the plurality of electrodes, and a half-blanking portion that has a concave portion formed in a thickness direction of the lead frame and a protrusion formed at a position corresponding to the concave portion, and which is covered with a sealing resin material that seals the semiconductor element. A stress-dispersing portion for dispersing stress that arises, when the half-blanking portion is formed, is provided in the corner portion.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus.

Abstract: A semiconductor device (10) comprises a die (11) provided between a first leadframe (12) and a second leadframe (13), such that a first surface of the die (11) is connected to the first leadframe (12) and a second surface of the die (11) is connected to a second leadframe (13). Mold compound (15) includes side recesses (16) into which end portions (18) of leadframe (12) can be fit.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: A lead frame includes: a die pad for holding a semiconductor chip; a radiator plate extending outward from one side face of the die pad and another side face thereof opposite the one side; a plurality of inner leads arranged opposite respective sides of the die pad other than the sides from which the radiator plate extends so as to interpose the die pad; and a plurality of outer leads formed outside the plurality of inner leads and connected to the inner leads. At least one of the plurality of inner leads serves as a ground lead connected to the die pad. In the radiator plate, an island bonding area of which potential is equal to that of the die pad is formed, a first slit is formed around three sides of the island bonding area, and the other side is connected to the radiator plate through a joint part.

Abstract: A semiconductor apparatus includes a semiconductor pellet having electrodes thereon; a plurality of lead terminals, which electrically connect the electrodes of the semiconductor pellet to terminals formed on a substrate; and a molding member, which is filled around the semiconductor pellet and upper parts of the lead terminals. The plurality of lead terminals are shaped to be elongated strips and are arranged to extend out of the molding member toward the substrate.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: A leadframe for a surface-mountable radiation-emitting component, preferably a light-emitting diode component, having at least one chip connection region and at least one external connection strip. The leadframe is formed in planar fashion and a deformation element, preferably a spring element, is arranged between the chip connection region and the external connection strip. The deformation element enables an elastic or plastic deformation of the leadframe in the plane of the leadframe. A housing, a surface-mountable component and an arrangement having a plurality of such components are furthermore specified.

Abstract: A surface mount package for a multi-chip device has a leadframe formed with first and second die pads and readouts from the respective die pads. An environmentally responsive sensor chip is secured to the first die pad and an environmentally isolated chip is secured to the second die pad. The chips are electrically coupled through the lead frame. A body formed with an over molded portion encases the isolated chip and an open molded portion formed with a recess receives the environmentally sensitive chip. An apertured cover is secured in the recess to form a protective covering over the sensor chip and for allowing communication of the sensor chip externally of the package.

Abstract: A system is provided for an integrated circuit package including a leadframe with a lead finger. A groove is in a lead finger for a conductive bonding agent and a passive device is in the groove to be held by the conductive bonding agent.