Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view.

Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package.

Abstract: A semiconductor device that can cope with larger numbers of pins and finer pitches while suppressing lowering of the manufacturing yield and reliability includes: a semiconductor chip having a plurality of electrodes provided on an upper surface thereof; a plurality of lead terminals including inner lead portions disposed toward the semiconductor chip; a sheet-form wiring member having a plurality of conductors insulated from one another on one main surface thereof; and a sealing-resin layer for sealing at least the semiconductor chip, the inner lead portions and the wiring member. The electrodes of the semiconductor device and the inner lead portions of the lead terminals are electrically connected respectively to each other via the conductors of the wiring member.

Abstract: An RF-coupled digital isolator includes a first leadframe portion and a second leadframe portion, electrically isolated from one another. The first leadframe portion includes a first main body and a first finger. The second leadframe portion includes a second main body and a second finger. The first main body is connected to a first ground, and the second main body is connected to a second ground that is electrically isolated from the first ground. The first finger and the second finger are electrically isolated from one another, e.g., by a plastic molding compound that forms a package for the digital isolator. The first finger acts as a primary of a transformer, and the second finger acts as a secondary of a transformer, when an RF signal drives to the first finger. The first finger and the second finger can be substantially parallel or anti-parallel to one another.

Abstract: In example embodiment, there is an integrated circuit (IC) device (5) assembled in a package (5) having a plurality of die including a first device (20) and at least one additional device (30). The IC comprises a substrate (10). A first device die (20), having bonding pads including ground connections, is die attached to the substrate (10). An additional device die (30), having bonding pads including ground connections is disposed on top of the first device die (20). The additional device die is die attached to the first device die. The ground connections of the first device die are connected to the ground connections of the additional device die in order to minimize the electrical interference between the device dies. An additional feature of the embodiment is, ground connections of the first device are connected to the ground connections of the additional device with a conductive adhesive (25).

Abstract: A semiconductor device has an IPD structure formed over a substrate. First and second electrical devices are mounted to a first surface of the IPD structure. An encapsulant is deposited over the first and second electrical devices and IPD structure. A shielding layer is formed over the encapsulant and electrically connected to a conductive channel in the IPD structure. The conductive channel is connected to ground potential to isolate the first and second electrical devices from external interference. A recess can be formed in the encapsulant material between the first and second electrical devices. The shielding layer extends into the recess. An interconnect structure is formed on a second surface of the IPD structure. The interconnect structure is electrically connected to the first and second electrical devices and IPD structure. A shielding cage can be formed over the first electrical device prior to depositing encapsulant.

Abstract: A semiconductor device, including: a substrate having an upper face on which a first ground pad, a first power supply pad, a first signal pad, and a second signal pad are formed; a first substrate formed on the substrate and having an upper face on which a third signal pad connected to the first signal pad and a first circuit are formed; and a semiconductor element including a second substrate having a reverse face on which a bump electrode connected to the first circuit and a second circuit are formed and an upper face on which a fourth signal pad connected to the second signal pad is formed, with a signal through via connected to the second circuit and the fourth signal pad being buried in the second substrate.

Abstract: Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with at least one die through electrically conducting bumps or balls and electrically conducting ribbons. Embodiments of the present invention may permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint.

Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.

Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.

Abstract: Disclosed in this specification is a buck converter package with stacked dice and a process for forming a buck converter. The package includes a die attach pad with a low side die mounted on one surface and a high side die mounted on the opposing surface. The die attach pad is conductive, such that the drain of the low side die is connected to the source of the high side die through the pad. A controller die controls the gates of the high and low side dies. A plurality of leads extends outside of the package to permit electrical connections to the inside of the package. The high side drain is exposed to one of the surfaces of the package.

Abstract: A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element including a magnetic body is electrically connected to the second conductive elements. The semiconductor package body or the energy storage element has a plurality of first conductive elements to be electrically connected to an outside device. The shielding layer is disposed between the control component and at least part of the magnetic body to inhibit or reduce EMI (Electro-Magnetic Interference) from the energy storage element and to get a tiny package structure. The three-dimensional package structure is applicable to a POL (Point of Load) converter.

Abstract: Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.

Abstract: A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ?5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites.

Abstract: A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity.

Abstract: A novel semiconductor device high in both heat dissipating property and connection reliability in mounting is to be provided. The semiconductor device comprises a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.

Abstract: A semiconductor chip package is provided. The semiconductor chip package includes a lead frame having a chip carrier. A semiconductor chip is mounted on the chip carrier, having a plurality of bonding pads thereon. A package substrate has a cavity therein to accommodate the chip carrier and the semiconductor chip, wherein at least one of the bonding pads of the semiconductor chip is electrically coupled to the package substrate.

Abstract: According to one embodiment, a semiconductor device includes: a lead group including a plurality of leads; a plurality of semiconductor memory chips stacked in a step shape on the lead group; and a resin mold section that seals the semiconductor memory chips. One end of a third lead and the other end of a second lead is connected by a metal wire for relay crossing over a first lead section included in the lead group. The metal wire for relay is provided in a space between the semiconductor memory chips stacked in the step shape and the lead group.

Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: A lead frame structure for supporting a semiconductor die is disclosed that includes at least two electrical leads each having a plurality of finger shaped structures unilaterally extending outward from the at least two electrical leads. The electrical leads are arranged so that the plurality of finger shaped structures forms inter-digital patterns where the semiconductor dies are bonded to the lead frame structure.

Abstract: An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.

Abstract: Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer.

Abstract: A lead frame assembly includes at least one die paddle. The die paddle includes a first landing area for receiving a first semiconductor chip and a second landing area for receiving a second semiconductor chip. One or more steps are provided between the first landing area and the second landing area.

Abstract: In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material 15 which is a die bonding material for bonding a semiconductor element 13 to a semiconductor substrate 11 is a Bi alloy containing 0.8 wt % to 10 wt % of Cu and 0.02 wt % to 0.2 wt % of Ge, so that the bonding material 15 for bonding the semiconductor element 13 to the semiconductor substrate 11 is not melted when the semiconductor device is bonded to the motherboard by reflowing. It is therefore possible to suppress poor connection on the semiconductor element 13, thereby securing the mountability and electrical reliability of the semiconductor device.

Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

Abstract: Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.

Abstract: A disclosed semiconductor device includes a wiring board, a semiconductor element mounted on a principal surface of the wiring board with flip chip mounting, a first conductive pattern formed on the principal surface along at least an edge portion of the semiconductor element, a second conductive pattern formed on the principal surface along the first conductive pattern and away from the first conductive pattern, a passive element bridging between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board, and a resin layer filling a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board.

Abstract: In an embodiment, the invention provides a coil transducer isolator package comprising at least one lead frame, at least two integrated circuits (ICs) and a flex circuit comprising at least a first coil transducer. The first coil transducer comprises at least one metal coil. The coil transducer isolator package is fabricated such that no portion of the lead frame is physically located within a spatial volume extending substantially perpendicular to the at least one metal coil. The boundaries of the spatial volume are defined by a periphery of the at least one metal coil. At least one of the two ICs is at least partially located within the spatial volume extending substantially perpendicular to the at least one metal coil.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a conductive layer having a first surface and a second surface; forming first concave trenches in the first surface of the conductive layer and the first concave trenches are connected by a first flat region of the first surface; connecting an integrated circuit to the first flat region with a conductive interconnect; encapsulating the integrated circuit with an encapsulation that fills the first concave trenches; and forming second concave trenches having a similar size in the second surface of the conductive layer with the second concave trenches connected by a second flat region that is larger than the first flat region, and the second concave trenches are formed through the conductive layer to expose the encapsulation.

Abstract: In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package.

Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.

Abstract: Semiconductor chip packages have die asymmetrically arranged on the respective substrates. Two such packages having complementary arrangements can be stacked, one inverted with respect to the other, such that the two die are situated side-by-side in the space between the two substrates. Also, multipackage modules include stacked packages, each having the die asymmetrically arranged on the substrate. Adjacent stacked packages have complementary asymmetrical arrangements of the die, and one package is inverted with respect to the other in the stack, such that the two die are situated side-by-side in the space between the two substrates. Also, methods are disclosed for making the packages and for making the stacked package modules.

Abstract: A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.

Abstract: A light emitting diode manufacturing method introduces a transparent enclosure to improve the uniformity of coating phosphor, so as to achieve the purposes of enhancing the uniform color temperature and the light emitting efficiency. The manufacturing method is used extensively for packaging various types of light emitting diode chips and mass production.

Abstract: A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad.

Abstract: An integrated circuit package system includes: forming a die-attach paddle, an outer interconnect, and an inner interconnect toward the die-attach paddle beyond the outer interconnect; mounting an integrated circuit device over the die-attach paddle; connecting the integrated circuit device to the inner interconnect and the outer interconnect; encapsulating the integrated circuit device over the die-attach paddle; attaching an external interconnect under the outer interconnect; and attaching a circuit device under the die-attach paddle and extended laterally beyond opposite sides of the die-attach paddle.

Abstract: A power semiconductor device includes a conductive board and a switching element mounted on the conductive board and electrically connected thereto. The power semiconductor device also includes an integrated circuit mounted on the conductive board at a distance from the switching element and electrically connected thereto. The switching element turns ON/OFF a connection between first and second main electrodes in response to a control signal inputted to a control electrode. The integrated circuit includes a control circuit which controls ON/OFF the switching element and a back side voltage detection element which detects a voltage of the back side of the integrated circuit.

Abstract: A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ?5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites.

Abstract: Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: A semiconductor chip package is disclosed. The semiconductor chip package comprises a lead frame having a chip carrier, wherein the chip carrier has a first surface and an opposite second surface. A semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the semiconductor chip has an area larger than that of the chip carrier. A package substrate comprises a central region attached to the second surface, having an area larger than that of the semiconductor chip, wherein some of the bonding pads of the semiconductor chip are electrically connected to a marginal region of the package substrate.

Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: A lead frame and a light emitting device package using the same are disclosed. More particularly, a lead frame and a light emitting device package using the lead frame which can be easily manufactured and employ a multi-chip structure. The light emitting device package includes a first frame including a heat sink, a second frame coupled to an upper side of the first frame, the second frame including at least one pair of leads and a mount formed with a hole, and a molded structure for coupling the first and second frames to each other.

Abstract: An integrated circuit pad structure includes a ground strip (206) positioned below a pad (101). In one example a conductive element (102) is coupled to the pad (101), and at least two tiled layers, positioned below the first conductive element (102) and positioned above the ground strip (206) are included. A conductor (203), may run beneath the ground strip (206). In a second example, a pad (101) is seated on a ground shield cage having a bottom conductive ground element (302) including several ground strips where at least one ground strip (116) is along a signal routing path. The ground shield cage further includes a set of stacked conductive ground elements, stacked to form sidewalls (209, 210) of the cage. The top conductive ground element (301) of the stacked elements has an inner perimeter and an outer perimeter, such that the inner perimeter surrounds the pad (101) and the top conductive ground element (301) is in the plane of the conductive element (102) coupled to the pad (101).

Abstract: An image processing system including an image processing device and a service providing device is provided. The image processing device includes a first processor and a first memory storing instructions that cause the image processing device to obtain parameters for receiving the service from the service providing device, request the service providing device to provide the service and implement a first or second function of the image processing device based on the parameters obtained from the parameter specifying unit. The service providing device includes a second processor and a second memory storing instructions that cause the service providing device to execute a service function to provide the service to the image processing device after receiving a request for the service from the image processing device.