Characterized By Materials Of Lead Frames Or Layers Thereon (epo) Patents (Class 257/E23.053)
  • Publication number: 20070001277
    Abstract: In one embodiment, a stack is assembled comprising a first integrated circuit package, and a substrate connector which connects the integrated circuit package to a circuit board. In one embodiment, the substrate connector includes an interposer substrate and a patch substrate bonded to the interposer substrate. Each substrate includes columnar conductors extending through the substrate to connect to another layer. Other embodiments are described and claimed.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventor: Kinya Ichikawa
  • Publication number: 20060281225
    Abstract: A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact and a plurality of source contacts, patterning a lead frame with target dimple areas, creating dimples in the lead frame corresponding to the gate contact and source contacts, printing a conductive epoxy on the lead frame in the dimples, curing the lead frame and semiconductor die wafer together, and dicing the wafer to form the semiconductor device packages.
    Type: Application
    Filed: June 9, 2005
    Publication date: December 14, 2006
    Inventors: Ming Sun, Demei Gong