Flexible Insulating Substrates (epo) Patents (Class 257/E23.065)
  • Publication number: 20110309491
    Abstract: A flexible semiconductor package is formed by interposing a flexible substrate between a tungsten stiffener and a die. A tungsten stiffener is bonded to a first surface of the flexible substrate prior to flip chip bonding or die attach of a die to a second surface of the flexible substrate. The tungsten stiffener is dimensioned so as to substantially overlap the die and provide a rigid and flat surface on which the die/flexible substrate bonding occurs. The flat and rigid characteristic of a tungsten stiffener optimizes the electrical and mechanical bond between the die and the flexible substrate as well as minimizing CTE mismatch.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: Sean Thorne, Scott Popelar
  • Patent number: 8039974
    Abstract: An electronic component assembly that has a supporting structure, an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors, the integrated circuit die and the PCB being mounted to the supporting structure by a die attach film such that they are adjacent and spaced from each other and, wire bonds electrically connecting the contact pads to the conductors. An intermediate portion of each of the wire bonds is adhered to the die attach film to lower the profile of the wire bond arcs.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 18, 2011
    Assignee: Silverbrook Research Pty Ltd
    Inventors: Kia Silverbrook, Laval Chung-Long-Shan, Kiangkai Tankongchumruskul
  • Patent number: 8035238
    Abstract: A tape carrier package (TCP) includes a film, a plurality of output leads and a plurality of input leads on the film, the plurality of output leads and the plurality of input leads being disposed on different sides, first and second TCP alignment marks arranged on opposing sides of the plurality of output leads, and a third TCP alignment mark at a central portion of the plurality of output leads.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: October 11, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Min-Hwa Kim, Jin-Cheol Hong
  • Patent number: 8026583
    Abstract: The invention relates to a flip-chip module with a semiconductor chip with contact posts, wherein the contact posts are connected electrically and mechanically to a substrate. Provided between the substrate and the semiconductor chip is a spacer, which is coupled mechanically to the substrate and/or the semiconductor chip. By this means, thermal stresses in the flip-chip module are absorbed by the spacer and kept away from the semiconductor chip. The invention also relates to a method for the production of a flip-chip module, in which firstly a spacer is located between the semiconductor chip and the substrate, after which the contact posts are soldered to the contact points of the substrate. Through the provision of the spacer the distance between the semiconductor chip and the substrate is set precisely, thereby improving the quality of the soldering points.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: September 27, 2011
    Assignee: HTC Beteiligungs GmbH
    Inventors: Ernst-A. Weissbach, Juergen Ertl
  • Patent number: 8017440
    Abstract: The reliability of a semiconductor device is enhanced. A first lead frame, a first semiconductor chip, a second lead frame, and a second semiconductor chip are stacked over an assembly jig in this order with solder in between and solder reflow processing is carried out to fabricate their assembly. Thereafter, this assembly is sandwiched between first and second molding dies to form an encapsulation resin portion. The upper surface of the second die is provided with steps. At a molding step, the second lead frame is clamped between the first and second dies at a position higher than the first lead frame; and a third lead frame is clamped between the first and second dies at a higher position. The assembly jig is provided with steps at the same positions as those of the steps in the upper surface of the second die in positions corresponding to those of the same.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichi Machida
  • Patent number: 7999341
    Abstract: A rectangular display driver integrated circuit device adapted for use with a flat panel display (FPD) device is disclosed and comprises, a plurality of input pads arranged in a central portion of the display driver integrated circuit device, and a plurality of output pads arranged along edges of all four sides of the display driver integrated circuit device. An associated film, film package, and flat panel display (FPD) module adapted to receive the display driver integrated circuit device are also disclosed.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ye-chung Chung, Sa-yoon Kang
  • Patent number: 7982296
    Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: July 19, 2011
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Publication number: 20110140264
    Abstract: There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region inside of an edge of the semiconductor package (FIG. 1).
    Type: Application
    Filed: February 10, 2011
    Publication date: June 16, 2011
    Inventor: TAKAO YAMAZAKI
  • Patent number: 7943491
    Abstract: The present invention provides methods, systems and system components for transferring, assembling and integrating features and arrays of features having selected nanosized and/or microsized physical dimensions, shapes and spatial orientations. Methods of the present invention utilize principles of ‘soft adhesion’ to guide the transfer, assembly and/or integration of features, such as printable semiconductor elements or other components of electronic devices. Methods of the present invention are useful for transferring features from a donor substrate to the transfer surface of an elastomeric transfer device and, optionally, from the transfer surface of an elastomeric transfer device to the receiving surface of a receiving substrate. The present methods and systems provide highly efficient, registered transfer of features and arrays of features, such as printable semiconductor element, in a concerted manner that maintains the relative spatial orientations of transferred features.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: May 17, 2011
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Patent number: 7939934
    Abstract: An assembly for testing microelectronic devices includes a microelectronic element having faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The assembly also includes a plurality of support elements disposed between the microelectronic element and the substrate for supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: May 10, 2011
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, David Gibson
  • Patent number: 7898074
    Abstract: A packaged electronic device includes a die, a flexible circuit structure, and a barrier film disposed on the die. The die includes die circuitry and electrical contacts. The flexible circuit structure is bonded directly to the die, and includes electrical conductors encapsulated by structural layers. Each electrical conductor contacts a respective electrical contact. The electronic device is encapsulated by the barrier film and one or more of the structural layers.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: March 1, 2011
    Inventors: Helmut Eckhardt, Stefan Ufer
  • Patent number: 7875969
    Abstract: A rigid-flex PCB includes at least one rigid PCB (RPCB) and at least one flexible PCB (FPCB). Each RPCB has a connection section; first and second sections separately extended from two lateral edges of the connection section and having at least one FPCB bonding side each; and a weakening structure formed along each joint of the connection section and the first and second sections. Each FPCB has a bending section corresponding to the connection section on the RPCB; first and second sections separately extended from two lateral edges of the bending section and having at least one RPCB bonding side each corresponding to the FPCB bonding sides of the first and second sections of the RPCB. When a proper pressure is applied against the weakening structures, the RPCB may be easily bent broken at the weakening structures to remove the connection section therefrom.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: January 25, 2011
    Assignee: Advanced Flexible Circuits Co., Ltd.
    Inventors: Kuo-Fu Su, Chih-Heng Chuo, Gwun-Jin Lin
  • Publication number: 20110012265
    Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.
    Type: Application
    Filed: June 2, 2010
    Publication date: January 20, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Hidenori Egawa
  • Publication number: 20100295045
    Abstract: A tape carrier package includes: a tape base; and interconnections formed on the tape base and extending to intersect a cutting line. At least a slit is formed along each of the interconnections, to intersect the cutting line and to divide the interconnection into a plurality of interconnection elements.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 25, 2010
    Applicant: Renesas Electronics Corporation
    Inventor: Isao Yoshino
  • Patent number: 7816778
    Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: October 19, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Choon Kuan Lee, Chong Chin Hui, David J. Corisis
  • Publication number: 20100244200
    Abstract: A wafer has a cutting part filled with a connecting medium. After the wafer is cut into chips along the cutting part, two contacts on two surfaces of the chip can be connected through corresponding leading wires and the connecting medium. Thus, the chip can have a flexible layout.
    Type: Application
    Filed: July 24, 2007
    Publication date: September 30, 2010
    Applicants: Chu, Tse Ming, Ma, Sung Chuan
    Inventors: Tse Ming Chu, Sung Chuan Ma
  • Publication number: 20100244281
    Abstract: Objects of the present invention is to provide a flexible printed wiring board which has a simple structure, which can be produced at low cost, and which can effectively dissipate heat generated by semiconductor chips, and to provide a semiconductor device employing the flexible printed wiring board. The flexible printed wiring board of the invention has an insulating substrate, and a wiring pattern formed of a conductor layer and provided on one surface of the insulating substrate, wherein the wiring pattern includes inner leads for mounting a semiconductor chip and outer leads for input and output wire connection, and a metal layer is adhered to the wiring pattern via an insulating adhesion layer.
    Type: Application
    Filed: March 30, 2010
    Publication date: September 30, 2010
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Katsuhiko HAYASHI, Tatsuo KATAOKA
  • Publication number: 20100244282
    Abstract: An electronic component assembly that has a supporting structure, an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors, the integrated circuit die and the PCB being mounted to the supporting structure by a die attach film such that they are adjacent and spaced from each other and, wire bonds electrically connecting the contact pads to the conductors. An intermediate portion of each of the wire bonds is adhered to the die attach film to lower the profile of the wire bond arcs.
    Type: Application
    Filed: June 10, 2010
    Publication date: September 30, 2010
    Inventors: Kia Silverbrook, Laval Chung-Long-Shan, Kiangkai Tankongchumruskul
  • Publication number: 20100244231
    Abstract: A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection.
    Type: Application
    Filed: October 22, 2008
    Publication date: September 30, 2010
    Applicant: NEC CORPORATION
    Inventors: Shintaro Yamamichi, Kentaro Mori, Hideya Murai
  • Patent number: 7800209
    Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Yukihiro Kozaka, Nozomi Shimoishizaka, Toshiyuki Fukuda
  • Publication number: 20100224986
    Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 9, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Toshiyuki Kojima, Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Shingo Komatsu
  • Patent number: 7776649
    Abstract: A method for fabricating a plurality of wafer level chip scale packages is revealed. A bumped wafer is laminated with a mold plate with a protection film placed thereon to partially embed the bumps of the wafer into the protection film and to form an underfill gap between the wafer and the protection film. By a first sawing step, the wafer fixed by the protection film is singulated into a plurality of chips having sides between the active surface and the back surface and also a filling gap is formed between the sides. Then, an encapsulant is formed on the protection film where the encapsulant fills the underfill gap through the filling gap to completely encapsulate the chips and the non-embedded portions of the bumps. By separating the encapsulant from the protection film and a second sawing step, the mold plate and the protection film are removed, and the encapsulant is singulated into a plurality of individual wafer level chip scale packages.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: August 17, 2010
    Assignee: Powertech Technology Inc.
    Inventor: Wen-Jeng Fan
  • Patent number: 7772109
    Abstract: A first multilayer wiring structural body 16 and a second multilayer wiring structural body 56 are simultaneously formed on both surfaces 101A, 101B of a substrate 101 and thereafter the portion of a structural body 120 corresponding to a third region C1 is folded so as to oppose a second structural body 22 to a second structural body 62 and the first multilayer wiring structural body 16 is electrically connected to the second multilayer wiring structural body 56.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: August 10, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yoshihiro Machida
  • Patent number: 7763986
    Abstract: A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: July 27, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-han Kim
  • Patent number: 7755178
    Abstract: A base semiconductor component for a semiconductor component stack is disclosed. In one embodiment, the base semiconductor component has a semiconductor chip arranged centrally on a stiff wiring substrate. The wiring substrate has, in its edge regions, contact pads which are electrically connected to external contacts and at the same time to contact areas of the semiconductor chip and also to stack contact areas. The stack contact areas simultaneously form the upper side of the base semiconductor component and have an arrangement pattern corresponding to an arrangement pattern of external contacts of a semiconductor component to be stacked.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: July 13, 2010
    Assignee: Infineon Technologies AG
    Inventors: Robert-Christian Hagen, Jens Pohl
  • Patent number: 7750446
    Abstract: Disclosed are IC package structures comprised of standard IC packages modified with separate circuit interconnection structures and disposed to interconnect either directly to other IC packages or to intermediate pedestal connectors which serve to support and interconnect various circuit elements, thus effectively allowing critical signals to bypass the generally less capable interconnection paths within standard interconnection substrates.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: July 6, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Gary Yasumura
  • Patent number: 7728422
    Abstract: One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed within the first through-hole; and a first external contact terminal within the first through-hole and electrically connecting the conductive pattern to the first semiconductor chip.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: June 1, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghan Kim, Kiwon Choi
  • Patent number: 7727809
    Abstract: The invention proposes a method and an apparatus for attaching a plurality of components having different arrangement densities or arrangement intervals, which can achieve shorter takt time. An object is to provide a low-cost manufacturing method of a semiconductor device and a manufacturing apparatus capable of manufacturing a semiconductor device at low cost. Plural pairs of components having different arrangement densities are simultaneously attached to each other by temporarily attaching first components to a first flexible substrate while changing an arrangement interval in an X direction, and then connecting the first components to second components over a second flexible substrate while changing an arrangement interval of the first components in a Y direction.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: June 1, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kyosuke Ito, Osamu Nakamura, Yukie Suzuki
  • Patent number: 7696614
    Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: April 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Hiroyuki Fukusako, Kazunori Seno
  • Publication number: 20100084665
    Abstract: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface.
    Type: Application
    Filed: May 26, 2009
    Publication date: April 8, 2010
    Inventors: John James Daniels, Gregory Victor Nelson
  • Patent number: 7682852
    Abstract: Provided is a method of manufacturing a semiconductor laser device having a light shield film comprising: forming a light emission structure by depositing a first clad layer, an active layer and a second clad layer on a substrate; depositing a light shield film and a protection film on the light emission face of the light emission structure; removing the light shield film corresponding to an area of the light emission face of the light emission structure including and above the first clad layer; and removing the protection layer.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: March 23, 2010
    Assignee: Samsung Led Co., Ltd.
    Inventors: Han-youl Ryu, Kyoung-ho Ha, Youn-joon Sung
  • Patent number: 7683471
    Abstract: A rectangular display driver integrated circuit device adapted for use with a flat panel display (FPD) device is disclosed and comprises, a plurality of input pads arranged in a central portion of the display driver integrated circuit device, and a plurality of output pads arranged along edges of all four sides of the display driver integrated circuit device. An associated film, film package, and flat panel display (FPD) module adapted to receive the display driver integrated circuit device are also disclosed.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ye-chung Chung, Sa-yoon Kang
  • Patent number: 7656014
    Abstract: A process yield of a semiconductor device is enhanced. To that end, there is provided a semiconductor device comprising a substrate having a component mount face with semiconductor chips mounted thereon, the substrate being provided with a plurality of connection leads, and a cap made of resin, placed over the component mount face of the substrate so as to cover the same, the a cap having a first body part, and a second body part larger in thickness than the first body part. Because product information in the form of inscriptions is engraved on the top surface side of the second body part of the cap, the product information can be displayed without the use of an ink mark, it is possible to prevent occurrence of marking defects due to ink bleed, and so forth, thereby enhancing the process yield of a memory card (the semiconductor device).
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: February 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yoshiyuki Tanigawa, Tamaki Wada
  • Patent number: 7649254
    Abstract: A structure is disclosed for connecting an electrically-connectable metal stiffener to a ground connection within a flexible substrate, the stiffener comprising nickel-gold plated stainless steel. In one embodiment the stiffener is secured to the flexible substrate by a non-conducting adhesive which includes an opening over a ground connection, the adhesive opening being filled by a conductive epoxy. A sequence for applying the disclosed materials discloses a method for attaching the stiffening structure to the flexible substrate.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: January 19, 2010
    Assignee: Flextronics AP, LLC
    Inventors: Bhret Graydon, Steve Frandrup
  • Publication number: 20090309214
    Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.
    Type: Application
    Filed: August 24, 2009
    Publication date: December 17, 2009
    Inventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman, Paul Goodwin
  • Patent number: 7622367
    Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: November 24, 2009
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Patent number: 7622800
    Abstract: A stackable semiconductor package and method includes providing a first semiconductor package having a first plurality of lower leads and a first plurality of upper leads. A second semiconductor package having a second plurality of lower leads is provided. The second plurality of lower leads is attached to the first plurality of upper leads to form a stack of semiconductor packages.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: November 24, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Kambhampati Ramakrishna, Il Kwon Shim, Seng Guan Chow
  • Patent number: 7615860
    Abstract: A rigid-flex PCB includes at least one rigid PCB (RPCB) and at least one flexible PCB (FPCB). Each RPCB has a connection section; first and second sections separately extended from two lateral edges of the connection section and having at least one FPCB bonding side each; and a weakening structure formed along each joint of the connection section and the first and second sections. Each FPCB has a bending section corresponding to the connection section on the RPCB; first and second sections separately extended from two lateral edges of the bending section and having at least one RPCB bonding side each corresponding to the FPCB bonding sides of the first and second sections of the RPCB. When a proper pressure is applied against the weakening structures, the RPCB may be easily bent broken at the weakening structures to remove the connection section therefrom.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: November 10, 2009
    Assignee: Advanced Flexible Circuits Co., Ltd.
    Inventors: Kuo-Fu Su, Chih-Heng Chuo, Gwun-Jin Lin
  • Patent number: 7608920
    Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: October 27, 2009
    Assignee: Entorian Technologies, LP
    Inventor: James Douglas Wehrly, Jr.
  • Patent number: 7605454
    Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allowed the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: October 20, 2009
    Assignee: Entorian Technologies, LP
    Inventor: James Douglas Wehrly, Jr.
  • Patent number: 7582959
    Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: September 1, 2009
    Assignee: Panasonic Corporation
    Inventor: Hiroyuki Fukusako
  • Patent number: 7582976
    Abstract: The present invention provides a semiconductor device tape carrier formed of an insulative tape 1 of a thin film, which becomes a semiconductor device by conducting a plurality of wire patterns 11 on its surface to a bump 23 of a semiconductor element 21 and being sealed by an insulative resin 22, wherein: an outer dimension of the semiconductor device in a carriage direction of the insulative tape 1 is greater than an integral multiple X (X=1, 2, 3, 4, 5, . . . ) of a pitch interval of sprocket holes 2, which are openings formed to carry the insulative tape 1, and not more than: the integral multiple X+a decimal Y (0<Y<1), and the tape pitch for a single semiconductor device is set to the integral multiple X+a decimal Y (0<Y<1).
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: September 1, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiharu Seko, Kenji Toyosawa
  • Patent number: 7579687
    Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: August 25, 2009
    Assignee: Entorian Technologies, LP
    Inventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman, Paul Goodwin
  • Patent number: 7554198
    Abstract: In some embodiments, flexible joint methodology to attach a die on an organic substrate is presented. In this regard, an integrated circuit chip package substrate is introduced having an organic substrate, an interposer coupled with a surface of the organic substrate, the interposer having cavities to accept bumps of a die, and a flexible tape layer coupled with a surface of the interposer, the flexible tape layer to couple with bumps of the die. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: June 30, 2009
    Assignee: Intel Corporation
    Inventors: Kazuo Ogata, Tsuyoshi Fukuo, Seiji Ishiyama, Tetsuhide Koh
  • Patent number: 7518238
    Abstract: A substrate may receive an integrated circuit and a flex circuit on the same side in the same vertical direction. In addition, in some embodiments, a flex circuit adapter and the integrated circuit may be surface mounted in one operation.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Henning Braunisch
  • Patent number: 7482698
    Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: January 27, 2009
    Assignee: Intel Corporation
    Inventors: Iwen Chao, Steve R. Eskildsen
  • Publication number: 20090020858
    Abstract: The present invention provides a tape carrier substrate that can prevent a conductor wire on the tape carrier substrate from being broken at the boundary portion between the conductor wire and a slit formed in a folding portion of the tape carrier substrate. The slit is formed in the folding portion of the tape carrier substrate so that the width thereof located on an extensional portion side of the tape carrier substrate is larger than that located on a central portion side of the tape carrier substrate. Possible stress resulting from bending of the tape carrier substrate is thus distributed. This prevents the stress from concentrating at the boundary portion between the slit and the conductor wire.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 22, 2009
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukihiro Kozaka, Yoshifumi Nakamura
  • Patent number: 7466021
    Abstract: Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: December 16, 2008
    Assignee: Interconnect Portfolio, LLP
    Inventor: Joseph Charles Fjelstad
  • Patent number: 7453157
    Abstract: A microelectronic package includes a microelectronic element having faces, contacts and an outer perimeter, and a flexible substrate overlying and spaced from a first face of the microelectronic element, an outer region of the flexible substrate extending beyond the outer perimeter of the microelectronic element. The package includes a plurality of etched conductive posts exposed at a surface of the flexible substrate and being electrically interconnected with the microelectronic element, wherein at least one of the conductive posts is disposed in the outer region of the flexible substrate, and a compliant layer disposed between the first face of the microelectronic element and the flexible substrate, wherein the compliant layer overlies the at least one of the conductive posts that is disposed in the outer region of the flexible substrate.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: November 18, 2008
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
  • Publication number: 20080251947
    Abstract: A COF flexible printed wiring board, used for a semiconductor device, contains an insulating layer, a wiring pattern formed of a conductor layer on one side of the insulating layer, on which a semiconductor chip is to be mounted, and a heat-resistant releasing layer, wherein the releasing layer is formed from a releasing agent and is provided on a surface of the insulating layer, which surface is opposite to the mounting side of the semiconductor chip, and the releasing layer and the insulating layer, as a whole, exhibit an optical transmittance of 50% or higher, excluding the area corresponding to the wiring pattern.
    Type: Application
    Filed: September 28, 2007
    Publication date: October 16, 2008
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Ken Sakata, Katsuhiko Hayashi