Flexible Insulating Substrates (epo) Patents (Class 257/E23.065)
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Publication number: 20110309491Abstract: A flexible semiconductor package is formed by interposing a flexible substrate between a tungsten stiffener and a die. A tungsten stiffener is bonded to a first surface of the flexible substrate prior to flip chip bonding or die attach of a die to a second surface of the flexible substrate. The tungsten stiffener is dimensioned so as to substantially overlap the die and provide a rigid and flat surface on which the die/flexible substrate bonding occurs. The flat and rigid characteristic of a tungsten stiffener optimizes the electrical and mechanical bond between the die and the flexible substrate as well as minimizing CTE mismatch.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Applicant: Aeroflex Colorado Springs Inc.Inventors: Sean Thorne, Scott Popelar
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Patent number: 8039974Abstract: An electronic component assembly that has a supporting structure, an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors, the integrated circuit die and the PCB being mounted to the supporting structure by a die attach film such that they are adjacent and spaced from each other and, wire bonds electrically connecting the contact pads to the conductors. An intermediate portion of each of the wire bonds is adhered to the die attach film to lower the profile of the wire bond arcs.Type: GrantFiled: June 10, 2010Date of Patent: October 18, 2011Assignee: Silverbrook Research Pty LtdInventors: Kia Silverbrook, Laval Chung-Long-Shan, Kiangkai Tankongchumruskul
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Patent number: 8035238Abstract: A tape carrier package (TCP) includes a film, a plurality of output leads and a plurality of input leads on the film, the plurality of output leads and the plurality of input leads being disposed on different sides, first and second TCP alignment marks arranged on opposing sides of the plurality of output leads, and a third TCP alignment mark at a central portion of the plurality of output leads.Type: GrantFiled: December 20, 2006Date of Patent: October 11, 2011Assignee: LG Display Co., Ltd.Inventors: Min-Hwa Kim, Jin-Cheol Hong
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Patent number: 8026583Abstract: The invention relates to a flip-chip module with a semiconductor chip with contact posts, wherein the contact posts are connected electrically and mechanically to a substrate. Provided between the substrate and the semiconductor chip is a spacer, which is coupled mechanically to the substrate and/or the semiconductor chip. By this means, thermal stresses in the flip-chip module are absorbed by the spacer and kept away from the semiconductor chip. The invention also relates to a method for the production of a flip-chip module, in which firstly a spacer is located between the semiconductor chip and the substrate, after which the contact posts are soldered to the contact points of the substrate. Through the provision of the spacer the distance between the semiconductor chip and the substrate is set precisely, thereby improving the quality of the soldering points.Type: GrantFiled: September 13, 2006Date of Patent: September 27, 2011Assignee: HTC Beteiligungs GmbHInventors: Ernst-A. Weissbach, Juergen Ertl
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Patent number: 8017440Abstract: The reliability of a semiconductor device is enhanced. A first lead frame, a first semiconductor chip, a second lead frame, and a second semiconductor chip are stacked over an assembly jig in this order with solder in between and solder reflow processing is carried out to fabricate their assembly. Thereafter, this assembly is sandwiched between first and second molding dies to form an encapsulation resin portion. The upper surface of the second die is provided with steps. At a molding step, the second lead frame is clamped between the first and second dies at a position higher than the first lead frame; and a third lead frame is clamped between the first and second dies at a higher position. The assembly jig is provided with steps at the same positions as those of the steps in the upper surface of the second die in positions corresponding to those of the same.Type: GrantFiled: October 6, 2010Date of Patent: September 13, 2011Assignee: Renesas Electronics CorporationInventor: Yuichi Machida
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Patent number: 7999341Abstract: A rectangular display driver integrated circuit device adapted for use with a flat panel display (FPD) device is disclosed and comprises, a plurality of input pads arranged in a central portion of the display driver integrated circuit device, and a plurality of output pads arranged along edges of all four sides of the display driver integrated circuit device. An associated film, film package, and flat panel display (FPD) module adapted to receive the display driver integrated circuit device are also disclosed.Type: GrantFiled: February 17, 2010Date of Patent: August 16, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ye-chung Chung, Sa-yoon Kang
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Patent number: 7982296Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.Type: GrantFiled: September 22, 2009Date of Patent: July 19, 2011Assignee: The Board of Trustees of the University of IllinoisInventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
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Publication number: 20110140264Abstract: There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region inside of an edge of the semiconductor package (FIG. 1).Type: ApplicationFiled: February 10, 2011Publication date: June 16, 2011Inventor: TAKAO YAMAZAKI
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Patent number: 7943491Abstract: The present invention provides methods, systems and system components for transferring, assembling and integrating features and arrays of features having selected nanosized and/or microsized physical dimensions, shapes and spatial orientations. Methods of the present invention utilize principles of ‘soft adhesion’ to guide the transfer, assembly and/or integration of features, such as printable semiconductor elements or other components of electronic devices. Methods of the present invention are useful for transferring features from a donor substrate to the transfer surface of an elastomeric transfer device and, optionally, from the transfer surface of an elastomeric transfer device to the receiving surface of a receiving substrate. The present methods and systems provide highly efficient, registered transfer of features and arrays of features, such as printable semiconductor element, in a concerted manner that maintains the relative spatial orientations of transferred features.Type: GrantFiled: June 9, 2006Date of Patent: May 17, 2011Assignee: The Board of Trustees of the University of IllinoisInventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
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Patent number: 7939934Abstract: An assembly for testing microelectronic devices includes a microelectronic element having faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The assembly also includes a plurality of support elements disposed between the microelectronic element and the substrate for supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements.Type: GrantFiled: December 22, 2005Date of Patent: May 10, 2011Assignee: Tessera, Inc.Inventors: Belgacem Haba, David Gibson
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Patent number: 7898074Abstract: A packaged electronic device includes a die, a flexible circuit structure, and a barrier film disposed on the die. The die includes die circuitry and electrical contacts. The flexible circuit structure is bonded directly to the die, and includes electrical conductors encapsulated by structural layers. Each electrical conductor contacts a respective electrical contact. The electronic device is encapsulated by the barrier film and one or more of the structural layers.Type: GrantFiled: December 12, 2008Date of Patent: March 1, 2011Inventors: Helmut Eckhardt, Stefan Ufer
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Patent number: 7875969Abstract: A rigid-flex PCB includes at least one rigid PCB (RPCB) and at least one flexible PCB (FPCB). Each RPCB has a connection section; first and second sections separately extended from two lateral edges of the connection section and having at least one FPCB bonding side each; and a weakening structure formed along each joint of the connection section and the first and second sections. Each FPCB has a bending section corresponding to the connection section on the RPCB; first and second sections separately extended from two lateral edges of the bending section and having at least one RPCB bonding side each corresponding to the FPCB bonding sides of the first and second sections of the RPCB. When a proper pressure is applied against the weakening structures, the RPCB may be easily bent broken at the weakening structures to remove the connection section therefrom.Type: GrantFiled: September 16, 2009Date of Patent: January 25, 2011Assignee: Advanced Flexible Circuits Co., Ltd.Inventors: Kuo-Fu Su, Chih-Heng Chuo, Gwun-Jin Lin
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Publication number: 20110012265Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.Type: ApplicationFiled: June 2, 2010Publication date: January 20, 2011Applicant: NEC Electronics CorporationInventor: Hidenori Egawa
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Publication number: 20100295045Abstract: A tape carrier package includes: a tape base; and interconnections formed on the tape base and extending to intersect a cutting line. At least a slit is formed along each of the interconnections, to intersect the cutting line and to divide the interconnection into a plurality of interconnection elements.Type: ApplicationFiled: May 19, 2010Publication date: November 25, 2010Applicant: Renesas Electronics CorporationInventor: Isao Yoshino
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Patent number: 7816778Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.Type: GrantFiled: February 20, 2007Date of Patent: October 19, 2010Assignee: Micron Technology, Inc.Inventors: Choon Kuan Lee, Chong Chin Hui, David J. Corisis
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Publication number: 20100244200Abstract: A wafer has a cutting part filled with a connecting medium. After the wafer is cut into chips along the cutting part, two contacts on two surfaces of the chip can be connected through corresponding leading wires and the connecting medium. Thus, the chip can have a flexible layout.Type: ApplicationFiled: July 24, 2007Publication date: September 30, 2010Applicants: Chu, Tse Ming, Ma, Sung ChuanInventors: Tse Ming Chu, Sung Chuan Ma
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Publication number: 20100244281Abstract: Objects of the present invention is to provide a flexible printed wiring board which has a simple structure, which can be produced at low cost, and which can effectively dissipate heat generated by semiconductor chips, and to provide a semiconductor device employing the flexible printed wiring board. The flexible printed wiring board of the invention has an insulating substrate, and a wiring pattern formed of a conductor layer and provided on one surface of the insulating substrate, wherein the wiring pattern includes inner leads for mounting a semiconductor chip and outer leads for input and output wire connection, and a metal layer is adhered to the wiring pattern via an insulating adhesion layer.Type: ApplicationFiled: March 30, 2010Publication date: September 30, 2010Applicant: MITSUI MINING & SMELTING CO., LTD.Inventors: Katsuhiko HAYASHI, Tatsuo KATAOKA
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Publication number: 20100244282Abstract: An electronic component assembly that has a supporting structure, an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors, the integrated circuit die and the PCB being mounted to the supporting structure by a die attach film such that they are adjacent and spaced from each other and, wire bonds electrically connecting the contact pads to the conductors. An intermediate portion of each of the wire bonds is adhered to the die attach film to lower the profile of the wire bond arcs.Type: ApplicationFiled: June 10, 2010Publication date: September 30, 2010Inventors: Kia Silverbrook, Laval Chung-Long-Shan, Kiangkai Tankongchumruskul
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Publication number: 20100244231Abstract: A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection.Type: ApplicationFiled: October 22, 2008Publication date: September 30, 2010Applicant: NEC CORPORATIONInventors: Shintaro Yamamichi, Kentaro Mori, Hideya Murai
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Patent number: 7800209Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.Type: GrantFiled: January 8, 2007Date of Patent: September 21, 2010Assignee: Panasonic CorporationInventors: Yukihiro Kozaka, Nozomi Shimoishizaka, Toshiyuki Fukuda
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Publication number: 20100224986Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.Type: ApplicationFiled: March 22, 2010Publication date: September 9, 2010Applicant: PANASONIC CORPORATIONInventors: Toshiyuki Kojima, Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Shingo Komatsu
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Patent number: 7776649Abstract: A method for fabricating a plurality of wafer level chip scale packages is revealed. A bumped wafer is laminated with a mold plate with a protection film placed thereon to partially embed the bumps of the wafer into the protection film and to form an underfill gap between the wafer and the protection film. By a first sawing step, the wafer fixed by the protection film is singulated into a plurality of chips having sides between the active surface and the back surface and also a filling gap is formed between the sides. Then, an encapsulant is formed on the protection film where the encapsulant fills the underfill gap through the filling gap to completely encapsulate the chips and the non-embedded portions of the bumps. By separating the encapsulant from the protection film and a second sawing step, the mold plate and the protection film are removed, and the encapsulant is singulated into a plurality of individual wafer level chip scale packages.Type: GrantFiled: May 1, 2009Date of Patent: August 17, 2010Assignee: Powertech Technology Inc.Inventor: Wen-Jeng Fan
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Patent number: 7772109Abstract: A first multilayer wiring structural body 16 and a second multilayer wiring structural body 56 are simultaneously formed on both surfaces 101A, 101B of a substrate 101 and thereafter the portion of a structural body 120 corresponding to a third region C1 is folded so as to oppose a second structural body 22 to a second structural body 62 and the first multilayer wiring structural body 16 is electrically connected to the second multilayer wiring structural body 56.Type: GrantFiled: March 15, 2007Date of Patent: August 10, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventor: Yoshihiro Machida
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Patent number: 7763986Abstract: A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.Type: GrantFiled: October 30, 2006Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-han Kim
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Patent number: 7755178Abstract: A base semiconductor component for a semiconductor component stack is disclosed. In one embodiment, the base semiconductor component has a semiconductor chip arranged centrally on a stiff wiring substrate. The wiring substrate has, in its edge regions, contact pads which are electrically connected to external contacts and at the same time to contact areas of the semiconductor chip and also to stack contact areas. The stack contact areas simultaneously form the upper side of the base semiconductor component and have an arrangement pattern corresponding to an arrangement pattern of external contacts of a semiconductor component to be stacked.Type: GrantFiled: February 23, 2005Date of Patent: July 13, 2010Assignee: Infineon Technologies AGInventors: Robert-Christian Hagen, Jens Pohl
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Patent number: 7750446Abstract: Disclosed are IC package structures comprised of standard IC packages modified with separate circuit interconnection structures and disposed to interconnect either directly to other IC packages or to intermediate pedestal connectors which serve to support and interconnect various circuit elements, thus effectively allowing critical signals to bypass the generally less capable interconnection paths within standard interconnection substrates.Type: GrantFiled: July 14, 2005Date of Patent: July 6, 2010Assignee: Interconnect Portfolio LLCInventors: Joseph C. Fjelstad, Kevin P. Grundy, Gary Yasumura
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Patent number: 7728422Abstract: One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed within the first through-hole; and a first external contact terminal within the first through-hole and electrically connecting the conductive pattern to the first semiconductor chip.Type: GrantFiled: December 18, 2007Date of Patent: June 1, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Donghan Kim, Kiwon Choi
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Patent number: 7727809Abstract: The invention proposes a method and an apparatus for attaching a plurality of components having different arrangement densities or arrangement intervals, which can achieve shorter takt time. An object is to provide a low-cost manufacturing method of a semiconductor device and a manufacturing apparatus capable of manufacturing a semiconductor device at low cost. Plural pairs of components having different arrangement densities are simultaneously attached to each other by temporarily attaching first components to a first flexible substrate while changing an arrangement interval in an X direction, and then connecting the first components to second components over a second flexible substrate while changing an arrangement interval of the first components in a Y direction.Type: GrantFiled: May 18, 2007Date of Patent: June 1, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kyosuke Ito, Osamu Nakamura, Yukie Suzuki
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Patent number: 7696614Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).Type: GrantFiled: December 15, 2008Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Hiroyuki Fukusako, Kazunori Seno
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Publication number: 20100084665Abstract: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface.Type: ApplicationFiled: May 26, 2009Publication date: April 8, 2010Inventors: John James Daniels, Gregory Victor Nelson
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Patent number: 7682852Abstract: Provided is a method of manufacturing a semiconductor laser device having a light shield film comprising: forming a light emission structure by depositing a first clad layer, an active layer and a second clad layer on a substrate; depositing a light shield film and a protection film on the light emission face of the light emission structure; removing the light shield film corresponding to an area of the light emission face of the light emission structure including and above the first clad layer; and removing the protection layer.Type: GrantFiled: August 9, 2007Date of Patent: March 23, 2010Assignee: Samsung Led Co., Ltd.Inventors: Han-youl Ryu, Kyoung-ho Ha, Youn-joon Sung
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Patent number: 7683471Abstract: A rectangular display driver integrated circuit device adapted for use with a flat panel display (FPD) device is disclosed and comprises, a plurality of input pads arranged in a central portion of the display driver integrated circuit device, and a plurality of output pads arranged along edges of all four sides of the display driver integrated circuit device. An associated film, film package, and flat panel display (FPD) module adapted to receive the display driver integrated circuit device are also disclosed.Type: GrantFiled: July 18, 2006Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ye-chung Chung, Sa-yoon Kang
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Patent number: 7656014Abstract: A process yield of a semiconductor device is enhanced. To that end, there is provided a semiconductor device comprising a substrate having a component mount face with semiconductor chips mounted thereon, the substrate being provided with a plurality of connection leads, and a cap made of resin, placed over the component mount face of the substrate so as to cover the same, the a cap having a first body part, and a second body part larger in thickness than the first body part. Because product information in the form of inscriptions is engraved on the top surface side of the second body part of the cap, the product information can be displayed without the use of an ink mark, it is possible to prevent occurrence of marking defects due to ink bleed, and so forth, thereby enhancing the process yield of a memory card (the semiconductor device).Type: GrantFiled: July 18, 2007Date of Patent: February 2, 2010Assignee: Renesas Technology Corp.Inventors: Yoshiyuki Tanigawa, Tamaki Wada
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Patent number: 7649254Abstract: A structure is disclosed for connecting an electrically-connectable metal stiffener to a ground connection within a flexible substrate, the stiffener comprising nickel-gold plated stainless steel. In one embodiment the stiffener is secured to the flexible substrate by a non-conducting adhesive which includes an opening over a ground connection, the adhesive opening being filled by a conductive epoxy. A sequence for applying the disclosed materials discloses a method for attaching the stiffening structure to the flexible substrate.Type: GrantFiled: May 1, 2006Date of Patent: January 19, 2010Assignee: Flextronics AP, LLCInventors: Bhret Graydon, Steve Frandrup
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Publication number: 20090309214Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.Type: ApplicationFiled: August 24, 2009Publication date: December 17, 2009Inventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman, Paul Goodwin
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Patent number: 7622367Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.Type: GrantFiled: June 2, 2005Date of Patent: November 24, 2009Assignee: The Board of Trustees of the University of IllinoisInventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
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Patent number: 7622800Abstract: A stackable semiconductor package and method includes providing a first semiconductor package having a first plurality of lower leads and a first plurality of upper leads. A second semiconductor package having a second plurality of lower leads is provided. The second plurality of lower leads is attached to the first plurality of upper leads to form a stack of semiconductor packages.Type: GrantFiled: June 8, 2007Date of Patent: November 24, 2009Assignee: Stats Chippac Ltd.Inventors: Kambhampati Ramakrishna, Il Kwon Shim, Seng Guan Chow
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Patent number: 7615860Abstract: A rigid-flex PCB includes at least one rigid PCB (RPCB) and at least one flexible PCB (FPCB). Each RPCB has a connection section; first and second sections separately extended from two lateral edges of the connection section and having at least one FPCB bonding side each; and a weakening structure formed along each joint of the connection section and the first and second sections. Each FPCB has a bending section corresponding to the connection section on the RPCB; first and second sections separately extended from two lateral edges of the bending section and having at least one RPCB bonding side each corresponding to the FPCB bonding sides of the first and second sections of the RPCB. When a proper pressure is applied against the weakening structures, the RPCB may be easily bent broken at the weakening structures to remove the connection section therefrom.Type: GrantFiled: April 19, 2007Date of Patent: November 10, 2009Assignee: Advanced Flexible Circuits Co., Ltd.Inventors: Kuo-Fu Su, Chih-Heng Chuo, Gwun-Jin Lin
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Patent number: 7608920Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.Type: GrantFiled: May 16, 2006Date of Patent: October 27, 2009Assignee: Entorian Technologies, LPInventor: James Douglas Wehrly, Jr.
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Patent number: 7605454Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allowed the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.Type: GrantFiled: February 1, 2007Date of Patent: October 20, 2009Assignee: Entorian Technologies, LPInventor: James Douglas Wehrly, Jr.
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Patent number: 7582959Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).Type: GrantFiled: March 11, 2005Date of Patent: September 1, 2009Assignee: Panasonic CorporationInventor: Hiroyuki Fukusako
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Patent number: 7582976Abstract: The present invention provides a semiconductor device tape carrier formed of an insulative tape 1 of a thin film, which becomes a semiconductor device by conducting a plurality of wire patterns 11 on its surface to a bump 23 of a semiconductor element 21 and being sealed by an insulative resin 22, wherein: an outer dimension of the semiconductor device in a carriage direction of the insulative tape 1 is greater than an integral multiple X (X=1, 2, 3, 4, 5, . . . ) of a pitch interval of sprocket holes 2, which are openings formed to carry the insulative tape 1, and not more than: the integral multiple X+a decimal Y (0<Y<1), and the tape pitch for a single semiconductor device is set to the integral multiple X+a decimal Y (0<Y<1).Type: GrantFiled: September 6, 2007Date of Patent: September 1, 2009Assignee: Sharp Kabushiki KaishaInventors: Toshiharu Seko, Kenji Toyosawa
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Patent number: 7579687Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.Type: GrantFiled: January 13, 2006Date of Patent: August 25, 2009Assignee: Entorian Technologies, LPInventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman, Paul Goodwin
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Patent number: 7554198Abstract: In some embodiments, flexible joint methodology to attach a die on an organic substrate is presented. In this regard, an integrated circuit chip package substrate is introduced having an organic substrate, an interposer coupled with a surface of the organic substrate, the interposer having cavities to accept bumps of a die, and a flexible tape layer coupled with a surface of the interposer, the flexible tape layer to couple with bumps of the die. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 29, 2006Date of Patent: June 30, 2009Assignee: Intel CorporationInventors: Kazuo Ogata, Tsuyoshi Fukuo, Seiji Ishiyama, Tetsuhide Koh
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Patent number: 7518238Abstract: A substrate may receive an integrated circuit and a flex circuit on the same side in the same vertical direction. In addition, in some embodiments, a flex circuit adapter and the integrated circuit may be surface mounted in one operation.Type: GrantFiled: December 2, 2005Date of Patent: April 14, 2009Assignee: Intel CorporationInventors: Daoqiang Lu, Henning Braunisch
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Patent number: 7482698Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.Type: GrantFiled: September 22, 2006Date of Patent: January 27, 2009Assignee: Intel CorporationInventors: Iwen Chao, Steve R. Eskildsen
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Publication number: 20090020858Abstract: The present invention provides a tape carrier substrate that can prevent a conductor wire on the tape carrier substrate from being broken at the boundary portion between the conductor wire and a slit formed in a folding portion of the tape carrier substrate. The slit is formed in the folding portion of the tape carrier substrate so that the width thereof located on an extensional portion side of the tape carrier substrate is larger than that located on a central portion side of the tape carrier substrate. Possible stress resulting from bending of the tape carrier substrate is thus distributed. This prevents the stress from concentrating at the boundary portion between the slit and the conductor wire.Type: ApplicationFiled: July 8, 2008Publication date: January 22, 2009Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yukihiro Kozaka, Yoshifumi Nakamura
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Patent number: 7466021Abstract: Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.Type: GrantFiled: May 2, 2006Date of Patent: December 16, 2008Assignee: Interconnect Portfolio, LLPInventor: Joseph Charles Fjelstad
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Patent number: 7453157Abstract: A microelectronic package includes a microelectronic element having faces, contacts and an outer perimeter, and a flexible substrate overlying and spaced from a first face of the microelectronic element, an outer region of the flexible substrate extending beyond the outer perimeter of the microelectronic element. The package includes a plurality of etched conductive posts exposed at a surface of the flexible substrate and being electrically interconnected with the microelectronic element, wherein at least one of the conductive posts is disposed in the outer region of the flexible substrate, and a compliant layer disposed between the first face of the microelectronic element and the flexible substrate, wherein the compliant layer overlies the at least one of the conductive posts that is disposed in the outer region of the flexible substrate.Type: GrantFiled: May 27, 2005Date of Patent: November 18, 2008Assignee: Tessera, Inc.Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
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Publication number: 20080251947Abstract: A COF flexible printed wiring board, used for a semiconductor device, contains an insulating layer, a wiring pattern formed of a conductor layer on one side of the insulating layer, on which a semiconductor chip is to be mounted, and a heat-resistant releasing layer, wherein the releasing layer is formed from a releasing agent and is provided on a surface of the insulating layer, which surface is opposite to the mounting side of the semiconductor chip, and the releasing layer and the insulating layer, as a whole, exhibit an optical transmittance of 50% or higher, excluding the area corresponding to the wiring pattern.Type: ApplicationFiled: September 28, 2007Publication date: October 16, 2008Applicant: MITSUI MINING & SMELTING CO., LTD.Inventors: Ken Sakata, Katsuhiko Hayashi