Abstract: One aspect of the invention pertains to a semiconductor package suitable for use in high stress environments, such as ones involving high pressures, temperatures and/or corrosive substances. In this aspect, a die and leadframe are fully encapsulated in a first plastic casing. The first plastic casing is fully encapsulated in turn with a second plastic casing. The two casings have different compositions. The first plastic casing, for example, may be made of a thermoset plastic material and the second plastic casing may be made of a thermoplastic material. The first plastic casing may have recesses, indentations and/or slots suitable for securing it to the second plastic casing. In some embodiments, a corrosion resistant coating is added to the second plastic casing. Methods for forming semiconductor packages suitable for use in high stress environments are also described.

Abstract: There are provided the steps of connecting a chip component 13 to a first substrate 10 through a wire 14, providing an electrode 21 on a second substrate 20, attaching, to the first substrate 10, a molding tool 30 having a protruded portion 31 formed corresponding to an array of a bump connecting pad 12 of the first substrate 10 and a cavity 32 formed corresponding to a region in which the chip component 13 is mounted, thereby forming a first sealing resin 34 for sealing the chip component 13 and the wire 14, bonding the electrode 21 to the bump connecting pad 12 through a solder, thereby bonding the first substrate 10 to the second substrate 20, and filling a second filling resin 40 in a clearance portion between the first substrate 10 and the second substrate 20.

Abstract: An apparatus on a wafer, comprising; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising; one or more base frames, a fourth metal layer of the wall comprising; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising; one or more top frames each over the pass-thru; and a metal lid.

Abstract: A method of manufacturing a light emitting display including an image display part formed on a substrate and a pad part including at least one terminal electrically connected to the image display part. The method includes forming thin film transistors and at least one electroluminescent device electrically connected to the thin film transistors and including a first electrode layer, an emission layer, and a second electrode layer on the image display part, forming a protection layer on the second electrode layer of the electroluminescent device and the pad part, sealing the image display part on the protection layer, and removing the protection layer formed at least on the pad part to expose the terminals. Therefore, it is possible to easily remove the protection layer formed of organic material or inorganic material formed on the pad part without an additional mask.

Abstract: A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are sealed by the first sealing material and the second sealing material.

Abstract: A semiconductor device manufacturing method includes (a) bonding a first surface of a metal plate to a substrate, (b) forming a plurality of metal posts that are arranged in vertical and lateral directions in a plan view and include a first metal post and a second metal post, by partially etching the metal plate bonded to the substrate from a second surface of the metal plate, (c) fixing an integrated circuit (IC) element to the second surface of the first metal post, (d) coupling the second metal post and a pad terminal of the integrated circuit element via a conductive material, (e) resin-sealing the integrated circuit element, the metal posts, and the conductive material by providing a resin onto the substrate, and (f) removing the substrate from the resin and the first surfaces of the metal posts sealed using the resin.

Abstract: In some embodiments, an apparatus and a system are provided. The apparatus and the system may comprise a first integrated circuit die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die comprising a second surface activated bonding site coupled to the first surface activated bonding site. The first surface activated bonding site may comprise a first clean metal and the second surface activated bonding site may comprise a second clean metal. If the first surface activated bonding site is coupled to the second surface activated bonding site respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.

Abstract: Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.

Abstract: The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a flexed microelectronic die mounted to the support member. The flexed microelectronic die has a plurality of terminals electrically coupled to the support member and an integrated circuit operably coupled to the terminals. The die can be a processor, memory, imager, or other suitable die. The support member can be a lead frame, a plurality of electrically conductive leads, and/or an interposer substrate.

Abstract: A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps is formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.

Abstract: An integrated package system with die and package combination including forming a leadframe having internal leads and external leads, encapsulating a first integrated circuit on the leadframe, and encapsulating a second integrated circuit over the first integrated circuit.

Abstract: A semiconductor device is provided, which comprises: a die including an active surface; a multiplicity of bond pads formed on the active surface of the die, wherein a first one of the bond pads is larger than a second one of the bond pads; and a multiplicity of solder bumps, each formed over a corresponding bond pad, wherein the multiplicity of solder bumps include a first solder bump formed over the first bond pad and a second solder bump formed over the second bond pad, the first solder bump having a footprint that is substantially larger than the second solder bump and a maximum diameter that is substantially larger than the second solder bump.

Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.

Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

Abstract: A method of fabricating a lead frame for a semiconductor device having a semiconductor chip resin-sealed therein. The lead frame includes a lead to be electrically connected to the semiconductor chip within sealing resin and to be sealed into the sealing resin such that at least a part of its mounting surface is exposed from the sealing resin. The method includes a lead forming step for forming the lead, and a side edge coining step for subjecting a side edge of a sealed surface, which is a surface on the opposite side of the mounting surface, of the lead to coining processing from the side of the sealed surface, to form a slipping preventing portion. The slipping preventing portion is to project sideward from the lead and to have a slipping preventing surface between the mounting surface and the sealed surface of the lead.

Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.

Abstract: A resin layer covering a semiconductor chip on a wiring board is composed of a first resin layer and a second resin layer, wherein the first resin layer and the second resin layer differ in their plan view pattern, satisfying a relation of a<b, where “a” is difference in length in the direction from the center of the board towards the edges between the first resin layer and the second resin layer, and “b” is difference in length in the direction from the center of the board towards the corners between the first resin layer and the second resin layer.

Abstract: Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die are first coated with a buffer region having a lower dielectric constant ? and/or lower loss tangent ? than the plastic encapsulation. The encapsulation surrounds the buffer region providing a solid structure. The lower ? buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower ? buffer region reduces the parasitic loss in the encapsulation. Low ? and/or ? buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has ? less than about 3.0 and/or ? less than about 0.005.

Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.

Abstract: A structure and method of forming a semiconductor material wafer comprising forming an ingot of semiconductor material. A first dielectric layer is formed on the surface of the ingot, and the surface of the first dielectric layer is larger than the surface of the ingot. A second dielectric layer is formed on the surface of the first dielectric layer, and the surface of the second dielectric layer is larger than the surface of the first dielectric layer. The semiconductor wafer structure comprises a slip core formed of a semiconductor material, a first annular portion, and a second annular portion. The slip core had a first outer peripheral. The first annular portion is adjacent to the first outer peripheral, and is formed of a first dielectric material. The first annular portion has a second outer peripheral being larger than the first outer peripheral. The second annular portion is adjacent to the second outer peripheral, and is formed of a second dielectric material.

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract: This publication discloses a method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components. According to the invention, through-holes for the semiconductor components are made in the base, in such a way that the holes extend between the first and second surface of the base. After the making of the holes, a polymer film is spread over the second surface of the base structure, in such a way that the polymer film also covers the through-holes made for the semiconductor components from the side of the second surface of the base structure. Before the hardening, or after the partial hardening of the polymer film, the semiconductor components are placed in the holes made in the base, from the direction of the first surface of the base.

Abstract: The invention relates to a semiconductor component for mounting on a printed circuit board. The semiconductor component includes a housing that at least partially surrounds at least one flat semiconductor chip. Electrical contacts are assigned to the semiconductor chip and serve to establish an electrical connection to electrodes provided on a printed circuit board. The flat semiconductor chip has a mounting lateral surface that includes contact surfaces configured to make contact with the electrical contacts. A buffer layer is located between the housing and the chip, and surrounds the chip up to a supporting surface located on the mounting lateral surface.

Abstract: A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.

Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.

Abstract: Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient of thermal expansion material and a high coefficient of thermal expansion material.

Abstract: A module includes a component, a circuit board having the component mounted thereon, a first grounding pattern formed on an outermost periphery of a surface portion of the circuit board; a first sealer provided on the circuit board and having a dimension projected on the circuit board, and a metal film covering the sealer and connected to the grounding pattern. The dimension of the first dealer is smaller than an outside dimension of the circuit board. The first sealer is made of first resin and sealing the component. The module has a low profile and is adequately shielded.

Abstract: A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.