Containing Semiconductor Material, E.g., Polysilicon (epo) Patents (Class 257/E23.164)
  • Patent number: 11984418
    Abstract: A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 14, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vivek Swaminathan Sridharan, Christopher Daniel Manack, Nazila Dadvand, Salvatore Frank Pavone, Patrick Francis Thompson
  • Patent number: 8895435
    Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Publication number: 20140097541
    Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Lo Yueh LIN
  • Patent number: 8686486
    Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Toshihiko Saito
  • Patent number: 8633544
    Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 21, 2014
    Assignee: Halo LSI, Inc.
    Inventors: Kimihiro Satoh, Tomoko Ogura, Ki-Tae Park, Nori Ogura, Yoshitaka Baba
  • Patent number: 8598705
    Abstract: A composite substrate for a semiconductor chip includes a first covering layer containing a semiconductor material, a second covering layer, and a core layer arranged between the first covering layer and the second covering layer, wherein the core layer has a greater coefficient of thermal expansion than the covering layers.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 3, 2013
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Jürgen Moosburger, Peter Stauβ, Andreas Plöβl
  • Publication number: 20130240882
    Abstract: A die in accordance with various embodiments may include a metallization area located proximate an edge of the die, and an electrical connection connected to the metallization area and running from the metallization area to the edge, wherein the electrical connection is free from metal. A wafer in accordance with various embodiments may include a die region having a metallization area, a kerf region having an electric or electronic device, and an electrical connection connecting the electric or electronic device with the metallization area, wherein the electrical connection is free from metal.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Dietrich Bonart
  • Patent number: 8178861
    Abstract: A semiconductor device is comprised of a semiconductor substrate, conductive layers stacked above the semiconductor substrate, which is comprised of a conductive polysilicon, and a metal layer provided above the conductive layers. Both ends of the conductive layers have stairsteps respectively. The conductive layers are connected in series by a metal layer which is provided on the stairsteps. The conductive layers connected in series comprise a resistance element.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: May 15, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takuya Futatsuyama
  • Patent number: 8076665
    Abstract: A semiconductor device is comprised of a semiconductor substrate, conductive layers stacked above the semiconductor substrate, which is comprised of a conductive polysilicon, and a metal layer provided above the conductive layers. Both ends of the conductive layers have stairsteps respectively. The conductive layers are connected in series by a metal layer which is provided on the stairsteps. The conductive layers connected in series comprise a resistance element.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: December 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takuya Futatsuyama
  • Publication number: 20110121410
    Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.
    Type: Application
    Filed: January 27, 2011
    Publication date: May 26, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 7927905
    Abstract: A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: April 19, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eugene Michael Chow, Pengfei Qi
  • Publication number: 20110042811
    Abstract: A semiconductor device includes a semiconductor substrate, electrodes separated from each other and extending from a first main surface in the direction of depth of the semiconductor substrate, and an interconnect portion coupling the electrodes to each other and extending from the first main surface in the direction of depth of the semiconductor substrate without passing through the semiconductor substrate. One of the electrodes is a through electrode passing through the semiconductor substrate to reach a second main surface. For semiconductor devices having through electrodes and vertically stacked on each other, the interconnect portion serves to enhance the degree of design freedom.
    Type: Application
    Filed: June 1, 2010
    Publication date: February 24, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Mika OKUMURA, Makio HORIKAWA, Takeshi MURAKAMI
  • Publication number: 20110018109
    Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
    Type: Application
    Filed: May 20, 2010
    Publication date: January 27, 2011
    Applicant: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
    Inventors: Volker Blaschke, Todd Thibeault, Chris Cureton, Paul Hurwitz, Arjun Kar-Roy, David Howard, Marco Racanelli
  • Patent number: 7829459
    Abstract: A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. The metal segments are arranged from the first end to the second end with the signals propagating from the second end to the first end. Where two metal segments are used, the segments have lengths of x = 2 ? ? L 7 and L-X where L is the length between the first end and the second end. Where three segments are used, the segments have lengths of X=0.25 L, Y=0.48 L, and Z=0.27 L.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: November 9, 2010
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Michael James Heinz
  • Publication number: 20100276804
    Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug fainted on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.
    Type: Application
    Filed: July 16, 2010
    Publication date: November 4, 2010
    Inventors: Jin-Hyock KIM, Jae-Sung Roh, Seung-Jin Yeom, Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim
  • Patent number: 7790580
    Abstract: The invention provides a method for forming thin film transistors including a polycrystalline semiconducting film. The method comprises depositing a first layer of amorphous semiconducting thin film on to a substrate; depositing a second layer of thin film on to the first layer of amorphous semiconducting thin film; patterning the second layer of thin film so that the first layer of amorphous semiconducting thin film is exposed at selected locations; exposing the first and second layers of thin film to a nickel containing compound in either a solution or a vapor phase; removing the second layer of thin film; and annealing the first layer of amorphous semiconducting thin film at an elevated temperature so the first layer of amorphous semiconducting thin film converts into a polycrystalline semiconducting thin film.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: September 7, 2010
    Assignee: Hong Kong University of Science and Technology
    Inventors: Hoi Sing Kwok, Man Wong, Zhiguo Meng, Shuyun Zhao, Chunya Wu
  • Patent number: 7705459
    Abstract: An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the lower interlayer insulating layer and has a via hole to expose the lower wire. The lower wire includes a metal layer pattern and a conductive layer pattern, and the metal layer pattern has a protruding portion and the conductive layer pattern is formed on the upper part of the protruding portion of the metal layer pattern and has a hole to expose the protruding portion.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: April 27, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang-Kwon Kim
  • Publication number: 20100065968
    Abstract: Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Suman K. Banerjee, Alain C. Duvallet, Olin L. Hartin, Craig Jasper, Walter Parmon
  • Publication number: 20100059888
    Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.
    Type: Application
    Filed: November 9, 2009
    Publication date: March 11, 2010
    Inventors: Yong-Kyu Lee, Hee-Seog JEON, Jeong-Uk HAN, Young-Ho Kim, Myung-Jo Chun
  • Publication number: 20100025773
    Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.
    Type: Application
    Filed: August 10, 2009
    Publication date: February 4, 2010
    Applicants: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Damien Lenoble, Philippe Coronel, Robin Cerutti
  • Patent number: 7592705
    Abstract: A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. The metal segments are arranged from the first end to the second end with the signals propagating from the second end to the first end. Where two metal segments are used, the segments have lengths of x = 2 ? L 7 and L?X where L is the length between the first end and the second end. Where three segments are used, the segments have lengths of X=0.25L, Y=0.48L, and Z=0.27L.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: September 22, 2009
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Michael James Heinz
  • Patent number: 7585757
    Abstract: In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Seon Ahn, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Eun-Kuk Chung, Hyung-Mo Yang, Chang-Yeon Yoo, Yun-Seung Kang, Kyung-Tae Jang
  • Publication number: 20090166872
    Abstract: A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. The memory device further includes a first layer of conductive strips forming a plurality of bit lines and a second layer of meal strips, the second layer of conductive strips overlying the polysilicon strips and coupled to the first group of polysilicon strips. In addition, the memory device includes a third layer of conductive strips forming one or more power line, and a fourth layer of metal strips, the fourth layer of conductive strips overlying the second layer of conductive strips and coupled to the second group of polysilicon strips to form a new word line structure having a low resistance.
    Type: Application
    Filed: April 10, 2008
    Publication date: July 2, 2009
    Inventors: Shine Chung, Cheng-Hsien Hung
  • Publication number: 20090108457
    Abstract: A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: Todd Alan Christensen, John Edward Sheets, II
  • Publication number: 20090032954
    Abstract: A semiconductor device includes a first insulation film having a plurality of openings which exposes predetermined regions of a semiconductor substrate, a plurality of first conductive patterns partially filling the openings and a plurality of second conductive patterns disposed on the first conductive patterns within the openings and separated from inner walls of the openings.
    Type: Application
    Filed: June 27, 2008
    Publication date: February 5, 2009
    Inventor: SANG-HO KIM
  • Publication number: 20080277736
    Abstract: A semiconductor device has an n-channel MISFET having first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including a first metal layer formed on the first gate insulating film, and a first n-type polysilicon film formed on the first metal layer, and a p-channel MISFET having second diffusion layers containing boron as a dopant and formed in a second region of the surface portion of the semiconductor substrate so as to sandwich a second channel region therebetween, a second gate insulating film formed on the second channel region, and a second gate electrode including a second metal layer containing nitrogen or carbon and formed on the second gate insulating film and a second n-type polysilicon film formed on the second metal layer and having a boron concentration of not more than 5×1019 cm?3 in a portion adjacent an in
    Type: Application
    Filed: May 1, 2008
    Publication date: November 13, 2008
    Inventor: Kazuaki NAKAJIMA
  • Publication number: 20080186763
    Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
    Type: Application
    Filed: March 31, 2008
    Publication date: August 7, 2008
    Inventors: Kimihiro Satoh, Tomoko Oguba, Ki-Tae Park, Nori Ogura, Yoshitaka Baba
  • Publication number: 20080157218
    Abstract: A semiconductor device including a semiconductor substrate having source/drain regions, a gate electrode formed on and/or over the semiconductor substrate, spacers formed against sidewalls of the gate electrode, an interlayer insulating layer formed over the semiconductor substrate and the gate electrode and having a plurality of contact holes formed therein, and contact plugs formed within the contact holes. The contact plugs can include a first contact plug and a second contact plug electrically connected to the gate electrode, and a third contact plug and a fourth contact plug electrically connected to the source/drain regions.
    Type: Application
    Filed: December 14, 2007
    Publication date: July 3, 2008
    Inventor: Jung-Ho Ahn
  • Publication number: 20080111246
    Abstract: A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. The metal segments are arranged from the first end to the second end with the signals propagating from the second end to the first end. Where two metal segments are used, the segments have lengths of x = 2 ? L 7 and L?X where L is the length between the first end and the second end. Where three segments are used, the segments have lengths of X=0.25 L, Y=0.48 L, and Z=0.27 L.
    Type: Application
    Filed: November 14, 2006
    Publication date: May 15, 2008
    Inventor: Michael James Heinz
  • Patent number: 7342301
    Abstract: A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: March 11, 2008
    Assignee: International Business Machines Corporation
    Inventors: David J. Frank, Kathryn W. Guarini, Christopher B. Murray, Xinlin Wang, Hon-Sum Philip Wong
  • Publication number: 20070228570
    Abstract: The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.
    Type: Application
    Filed: June 14, 2007
    Publication date: October 4, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christos Dimitrakopoulos, Stephen Gates, Vincent McGahay, Sanjay Mehta
  • Patent number: 7265437
    Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: September 4, 2007
    Assignees: International Business Machines Corporation, Sony Corporation
    Inventors: Son V. Nguyen, Sarah L. Lane, Eric G. Liniger, Kensaku Ida, Darryl D. Restaino
  • Patent number: 7176485
    Abstract: A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped region having a predetermined resistivity.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: February 13, 2007
    Assignee: International Business Machines Corporation
    Inventor: Robert K. Leidy
  • Patent number: 6794713
    Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Shigehiko Saida, Takeo Furuhata, Yoshitaka Tsunashima