Other Leads Being Parallel To Base (epo) Patents (Class 257/E23.185)
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Patent number: 11978682Abstract: A first frame is supported by a heat sink plate, surrounds an unmounted region of the heat sink plate, contains a resin, and has a first surface. A second frame contains a resin, and has a second surface opposing the first surface. An external terminal electrode passes between the first surface and the second surface. An adhesive layer contains a resin, and includes a lower portion, an upper portion, and an intermediate portion. The lower portion connects the external terminal electrode and the first surface to each other. The upper portion connects the external terminal electrode and the second surface to each other. The intermediate portion is disposed within a through hole of the external terminal electrode, and connects the lower portion and the upper portion to each other.Type: GrantFiled: November 19, 2021Date of Patent: May 7, 2024Assignees: NGK ELECTRONICS DEVICES, INC., NGK INSULATORS, LTD.Inventors: Yoshio Tsukiyama, Akiyoshi Osakada, Teppei Yamaguchi
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Patent number: 11948893Abstract: The disclosure is directed to an electronic device with a lid to manage radiation feedback. The electronic device includes a lid having at least one sidewall and a top wall, as well as a semiconductor positioned within a cavity of the lid. In certain embodiments, the lid includes at least one dielectric material and at least one internal conductive layer at least partially embedded within the at least one dielectric material. In certain embodiments, the lid includes dielectric material, as well as an internal wall extending from the top wall and positioned between an input port and an output port of the semiconductor. Such configurations may suppress any undesirable feedback through the lid between the input port and the output port of the semiconductor.Type: GrantFiled: December 21, 2021Date of Patent: April 2, 2024Assignee: Qorvo US, Inc.Inventors: Zhunming Du, Christopher Sanabria, Timothy M. Gittemeier, Terry Hon, Anthony Chiu, Tariq Lodhi
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Patent number: 11804414Abstract: An object is to provide a semiconductor device in which heat generated in a lead electrode when conducting a large current can be reduced and the bonding quality between the lead electrode and a semiconductor element can be inspected easily. A semiconductor device includes: a base portion; a semiconductor element mounted on the base portion; a metal part erect with respect to the semiconductor element and having one end bonded, with a bonding material, to a principal surface of the semiconductor element opposite to another principal surface of the semiconductor element mounted on the base portion; and a lead electrode connected to the semiconductor element through the metal part. The lead electrode includes a through hole extending in a thickness direction. The metal part connects the semiconductor element to the lead electrode, while inserted into the through hole of the lead electrode together with a part of the bonding material.Type: GrantFiled: January 4, 2022Date of Patent: October 31, 2023Assignee: Mitsubishi Electric CorporationInventors: Kazuhisa Osada, Yuki Yano, Satoru Ishikawa, Shohei Ogawa
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Patent number: 11587893Abstract: A distribution layer structure and a manufacturing method thereof, and a bond pad structure are provided. The distribution layer structure includes a dielectric layer and a wire layer embedded in the dielectric layer. The wire layer includes a frame and a connection line, the frame has at least two openings and is divided into a plurality of segments by the at least two openings. The connection line is located in the frame and has a plurality of connecting ends connected to the frame. The connection line divides an interior of the frame into a plurality of areas, with each segment connected to one of the connecting ends, and each area connected to one of the openings. This structure provides improved binding force between the wire layer and the dielectric layer without increasing a resistance of a wire connecting with a top bond pad.Type: GrantFiled: December 2, 2020Date of Patent: February 21, 2023Assignee: Changxin Memory Technologies, Inc.Inventors: Ping-Heng Wu, Chieh-Ting Hsu
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Patent number: 9006869Abstract: A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction.Type: GrantFiled: June 30, 2011Date of Patent: April 14, 2015Assignee: LG Innotek Co., Ltd.Inventor: JaeJoon Yoon
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Patent number: 8283769Abstract: A protective modular package cover has first and second fastening sections located at opposing first and second ends with one or more subassembly receiving sections disposed thereto and is configured to fasten the protective modular package cover to a core. Each fastening section has a foot surface located on a bottom surface of a fastening section and configured to make contact with the core, a mounting hole configured to receive a fastener, and a torque element. Each subassembly receiving section is configured to receive a subassembly and has a cross member formed along the underside of the protective modular package cover. Activation of the first torque element transfers a downward clamping force generated at the fastening element to a top surface of one or more subassemblies disposed in the one or more subassembly receiving sections via the cross member of each of the one or more subassembly receiving sections.Type: GrantFiled: October 13, 2010Date of Patent: October 9, 2012Assignee: STMicroelectronics, Inc.Inventors: Craig J. Rotay, John Ni, David Lam, David Lee DeWire, John W. Roman, Richard J. Ross
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Patent number: 7947534Abstract: An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; configuring each one of the plurality of leads to include first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and forming the second terminal ends of alternating leads disposed along the periphery of the package to form an etched lead-to-lead gap in excess of the predetermined interval gap.Type: GrantFiled: February 4, 2006Date of Patent: May 24, 2011Assignee: Stats Chippac Ltd.Inventors: Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Keng Kiat Lau
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Patent number: 7880283Abstract: A high reliability power module which includes a plurality of hermetically sealed packages each having electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.Type: GrantFiled: April 24, 2007Date of Patent: February 1, 2011Assignee: International Rectifier CorporationInventor: Weidong Zhuang
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Patent number: 7859110Abstract: The present invention provides a solder resist material, which can suppress the warpage of a semiconductor package upon exposure to heat or impact even when used in a thin wiring board and meets a demand for size reduction in electronic devices and a higher level of integration, and a wiring board comprising the solder resist material and a semiconductor package. The solder resist material of the present invention can effectively suppress the warpage of a semiconductor package through a fiber base material-containing layer interposed between resin layers. The fiber base material-containing layer is preferably unevenly distributed in the thickness direction of the solder resist material.Type: GrantFiled: April 26, 2007Date of Patent: December 28, 2010Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Kensuke Nakamura, Hiroshi Hirose
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Patent number: 7772679Abstract: This invention provides a magnetic shielding package structure of a magnetic memory device, in which at least a magnetic memory device is embedded between a magnetic shielding substrate and a magnetic shielding layer. A plurality of through vias is formed in the magnetic shielding substrate or the magnetic shielding layer, and a plurality of conductive contacts passes through the through vias such that electrical connection between the magnetic memory device and the external is established.Type: GrantFiled: June 23, 2008Date of Patent: August 10, 2010Assignee: Industrial Technology Research InstituteInventors: Shu-Ming Chang, Ying-Ching Shih
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Patent number: 7649250Abstract: Provided are a semiconductor package and a method for manufacturing the same. The semiconductor package includes: a substrate having a top surface on which a lead is formed and a bottom surface opposite to the top surface; a semiconductor chip attached to the top surface of the substrate and having an active surface on which a chip pad is formed and a back surface opposite to the active surface; a redistribution pattern electrically connected to the chip pad and extending from the active surface to a lateral surface of the semiconductor chip; and an interconnector electrically connecting the redistribution to the lead on the lateral surface of the semiconductor chip.Type: GrantFiled: November 14, 2007Date of Patent: January 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Tae-Sung Park
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Patent number: 7582964Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.Type: GrantFiled: November 19, 2007Date of Patent: September 1, 2009Assignee: Kyocera America, Inc.Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
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Patent number: 7298046Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluoroethylene, filled with fibers which may be glass fibers or ceramic fibers.Type: GrantFiled: January 10, 2003Date of Patent: November 20, 2007Assignee: Kyocera America, Inc.Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
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Patent number: 7262498Abstract: An assembly includes a substrate, a device coupled to the substrate; a ring formed on the substrate; and one or more bonding pads formed on the substrate, wherein the ring and bonding pads are formed of a same material.Type: GrantFiled: January 18, 2005Date of Patent: August 28, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: David M. Craig, Chien-Hua Chen, Charles C. Haluzak, Ronnie J. Yenchik