Container Being Hollow Construction And Having Insulating Or Insulated Base As Mounting For Semiconductor Body (epo) Patents (Class 257/E23.188)
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Patent number: 8912638Abstract: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.Type: GrantFiled: May 6, 2011Date of Patent: December 16, 2014Assignee: Infineon Technologies AGInventors: Horst Theuss, Gottfried Beer
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Patent number: 8624383Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.Type: GrantFiled: July 14, 2010Date of Patent: January 7, 2014Inventors: Yu-Lin Yen, Chen-Mei Fan
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Patent number: 8587107Abstract: A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures.Type: GrantFiled: February 9, 2010Date of Patent: November 19, 2013Assignee: Microsemi CorporationInventor: Tracy Autry
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Patent number: 8519531Abstract: An electrical and/or electronic device including: an electrical and/or electronic component; two layers of material forming front and back faces of the device and between which the electrical and/or electronic component is encapsulated, the component including at least two opposite faces placed facing the two layers of material; an electrical contact element placed in contact with one of the faces of the electrical and/or electronic component; an element based on at least one elastic material placed between one of the two layers of material and the electrical contact element, forming a first layer of elastic material covering the one of the two layers of material; and a second layer based on at least one elastic material with an elastic stiffness less than the stiffness of the elastic material in the first layer, placed in contact with the first layer of elastic material.Type: GrantFiled: December 14, 2010Date of Patent: August 27, 2013Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Eric Pilat, Alexandre Vachez
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Patent number: 8441117Abstract: In some aspects of the invention, an insulating substrate fixed onto a metal base plate can include an insulating plate and metal foils. A semiconductor element can be disposed on each of the metal foils. External connection terminals can be fixed to a set of ends of terminal holders, respectively. The other ends of the terminal holders can be bonded to the metal foils, respectively. External connection terminals which are main terminals through which main current flows are disposed on a lid. By preparing a plurality of lids having different layouts of the external connection terminals, in which the external connection terminals are connected to the terminal holders in the resin case, respectively, and exchanging the lids, the positions of the external connection terminals can be easily changed.Type: GrantFiled: February 9, 2012Date of Patent: May 14, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Shin Soyano
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Patent number: 8436464Abstract: A manufacturing method for a hollow sealing structure, includes, a process for filling a recessed portion in a principal surface of a substrate with a first sacrificial layer, a process for forming a functional element portion on the principal surface of the substrate, a process for forming a second sacrificial layer on the functional element portion so as to be connected to a part of the first sacrificial layer, a process for forming a covering portion over respective surfaces of the first and second sacrificial layers, a process for circulating a fluid for sacrificial layer removal through an opening in the covering portion in contact with the first sacrificial layer, thereby removing the first and second sacrificial layers, and a process for closing the opening.Type: GrantFiled: March 7, 2011Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Susumu Obata, Tatsuya Ohguro
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Publication number: 20120228755Abstract: A semiconductor module includes a high frequency chip, an insulating cap, a through electrode, interconnections, and an insulating layer. The insulating cap forms a hollow with the chip to cover the chip. The through electrode passes through a first plane of the cap and a second plane of the cap, the first plane facing the chip, the second plane being on a side opposite to the first plane. The interconnections are provided on the cap and connected to the through electrode. The insulating layer is provided on the cap and fills a portion between the interconnections therewith.Type: ApplicationFiled: September 18, 2011Publication date: September 13, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshihiko NAGANO, Hiroshi Yamada, Kazuhide Abe, Kazuhiko Itaya, Taihei Nakada
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Publication number: 20110227126Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Masaharu NAGAI, Osamu NAKAMURA
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Publication number: 20110180918Abstract: An arrangement comprising at least one power semiconductor module and a transport packaging, wherein the power semiconductor module has a base element, a housing and connection elements and the transport packaging has a generally planar cover layer, a cover film and at least one trough-like plastic shaped body for each power semiconductor module. The at least one plastic shaped body only partly encloses the respective power semiconductor module and a part of the plastic shaped body does not directly contact the power semiconductor module. Furthermore, a first side of the at least one power semiconductor module becomes situated directly or indirectly on the first main surface of the cover layer, while the cover film covers the further sides of the power semiconductor module directly and/or indirectly, and bears at least partly against the plastic shaped body.Type: ApplicationFiled: January 20, 2011Publication date: July 28, 2011Applicant: SEMIKRON Elektronik GmbH & Co. KGInventor: Stefan Starovecký
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Patent number: 7960829Abstract: A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member that substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.Type: GrantFiled: August 31, 2005Date of Patent: June 14, 2011Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Warren M. Farnworth, David R. Hembree, Sidney B. Rigg, William M. Hiatt, Peter Benson, Kyle K. Kirby, Salman Akram
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Patent number: 7936056Abstract: An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and the substrate, and configured to receive energy from an outside of the airtight sealed package, with the device sealed in the airtight manner in the airtight sealed package, to adjust pressure in the space. An energy transmission member transmits the energy to the pressure adjustment unit.Type: GrantFiled: January 23, 2008Date of Patent: May 3, 2011Assignee: Olympus CorporationInventor: Tomoyuki Hatakeyama
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Patent number: 7768124Abstract: A semiconductor sensor is contained in a cylindrical housing, an opening of which is closed with a cover member. The cover member includes a mounting plate integrally molded therewith. Components including a bare sensing chip and other circuit chips are directly mounted on a flat surface of the mounting plate. The components mounted on the flat surface are covered with gel having a high flowability. The gel is prevented from flowing out of the flat surface toward the cover member by banks formed at both sides of the flat surface. On an inner wall of the bank, curved surfaces and depressions are formed to surely suppress creeping up of the gel and to trap the gel therein if it creeps up the inner wall of the bank. Thus, the gel is surely prevented from flowing out even though the banks do not entirely surround the flat mounting surface.Type: GrantFiled: February 5, 2008Date of Patent: August 3, 2010Assignee: DENSO CORPORATIONInventor: Minoru Tokuhara
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Patent number: 7652385Abstract: Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.Type: GrantFiled: July 28, 2008Date of Patent: January 26, 2010Assignee: NEC Electronics CorporationInventor: Kazunori Kuramoto
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Patent number: 7635916Abstract: An IC package that employs top-side conduction cooling. The IC package has a low thermal resistance between a substrate housed within the package and the lid of the package. Thermal resistance is decreased by increasing the conduction cross-sections laterally through the package and lid and vertically from the package into the lid. The lid may also be modified with an extended mesa portion that reduces the gap between the lid and the IC. A thermally conductive spacer may also be interposed between the IC and the lid. Also, the package housing body and lid may be made from high thermal conductivity materials having thermal conductivities of 50 W/mK or greater with matching CTE between the lid and the package.Type: GrantFiled: March 23, 2007Date of Patent: December 22, 2009Assignee: Honeywell International Inc.Inventors: Ronald J. Jensen, Richard K. Spielberger
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Patent number: 7633151Abstract: Various integrated circuit packages, lids therefor and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing an integrated circuit package lid that has a surface adapted to face towards an integrated circuit, and forming a wetting film on the surface. The wetting film has at least one void where the surface of the lid is exposed. The void inhibits bonding so that a stress reduction site is produced.Type: GrantFiled: March 16, 2007Date of Patent: December 15, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Seah Sun Too, Jacquana Diep, Mohammad Khan
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Patent number: 7633150Abstract: A disclosed semiconductor device comprises a substrate, an element on the substrate and a sealing structure for sealing the element. The sealing structure has a structure such that a partition wall made of a metallic material formed on the substrate by a plating method so as to surround the element and a cap portion disposed on the partition wall are bonded via a bonding layer made of an inorganic material.Type: GrantFiled: July 10, 2006Date of Patent: December 15, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventor: Akinori Shiraishi
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Patent number: 7498669Abstract: A rectify element as a semiconductor device has a disk section, a first solder part, a buffer plate, a second solder part, a semiconductor chip, and a lead, and a sealing member with which the semiconductor chip is sealed. A cylindrical concave part is formed at one end surface of the disk section. A side wall of the cylindrical concave part faced to an inner peripheral wall at the upper surface of the disk section has a sloped shape of an angle of more than 90° to a contact surface of the upper surface of the disk section on which the semiconductor chip is placed.Type: GrantFiled: July 18, 2006Date of Patent: March 3, 2009Assignee: Denso CorporationInventor: Shigekazu Kataoka
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Publication number: 20080237839Abstract: A semiconductor apparatus and a method of manufacturing same can simplify the manufacturing process and prevent a decrease in production yield without decreasing in sensor sensitivity.Type: ApplicationFiled: March 14, 2008Publication date: October 2, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Yoshihiko Ino
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Publication number: 20080217709Abstract: A plurality of individual MEMS packages are formed as a contiguous unit and each of the plurality of individual MEMS packages include at least one acoustic port. One or more separation boundaries from where to separate adjacent ones of the plurality of individual MEMS packages are determined. Each of the plurality of individual MEMS packages are subsequently separated from the others according to the one or more separation boundaries to provide separate and distinct individual MEMS packages. Each acoustic port disposed within each separate and distinct individual MEMS package is exposed due to the separating so as to allow sound energy to enter each separate and distinct individual MEMS package.Type: ApplicationFiled: February 21, 2008Publication date: September 11, 2008Applicant: KNOWLES ELECTRONICS, LLCInventors: Anthony Minervini, Gwendolyn P. Massingill
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Publication number: 20080217761Abstract: The present invention provides a semiconductor device package comprising a substrate with at lease a pre-formed die receiving cavity formed and terminal contact metal pads formed within an upper surface of the substrate. At lease a first die is disposed within the die receiving cavity. A first dielectric layer is formed on the first die and the substrate and refilled into a gap between the first die and the substrate to absorb thermal mechanical stress there between. A first re-distribution layer (RDL) is formed on the first dielectric layer and coupled to the first die. A second dielectric layer is formed on the first RDL, and then a second die is disposed on the second dielectric layer and surrounded by core pastes having through holes thereon. A second re-distribution layer (RDL) is formed on the core pastes to fill the through holes, and then a third dielectric layer formed on the second RDL.Type: ApplicationFiled: March 8, 2007Publication date: September 11, 2008Inventors: Wen-Kun Yang, Chih-Ming Chen, Hsien-Wen Hsu
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Patent number: 7423333Abstract: A cerdip type of solid-state image sensing device includes a base on which photoelectric transfer devices are arranged in line along a main scanning direction, a sealed glass disposed on the base for fixing a lead frame, a wind frame disposed on the sealed glass, a transparent cover glass disposed on the wind frame, and a gripped surface for gripping the cerdip type of solid-state image sensing device.Type: GrantFiled: January 25, 2005Date of Patent: September 9, 2008Assignee: Ricoh Company, Ltd.Inventor: Yoshihiro Morii
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Publication number: 20080211087Abstract: A chip module comprises a substrate, a chip arranged on one side of the substrate and conductor structures arranged on at least one side of the substrate and conductively connected to the chip. At least one stiffening element is arranged on one side of the substrate and a moulding cap encapsulates at least the chip. For producing the chip module, provision is made for providing a substrate and applying conductor structures to at least one side of the substrate. At least one stiffening element is mounted onto one side of the substrate. Furthermore, a chip is mounted onto one side of the substrate and connected to the conductor structures. A moulding compound is applied on the substrate, such that the chip is covered.Type: ApplicationFiled: December 19, 2007Publication date: September 4, 2008Applicant: Infineon Technologies AGInventors: ANDREAS MUELLER-HIPPER, FRANK PUESCHNER
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Publication number: 20080191336Abstract: The invention discloses a subminiature electronic device with a hermetic cavity and method of manufacturing the same. It particularly relates to a chip type or chip scale packaged electronic device produced in substrate level. Firstly, a sacrificial layer is coated onto each of the identical microstructures disposed on a large substrate. A protective layer containing glass powders is then applied to encapsulate the sacrificial layer. Afterwards, the sacrificial layer is removed so as to form a cavity between the microstructure and the protective layer. The whole protective layer is then melted at elevated temperature to seal the cavity in an environment of specific gas. Finally, the large substrate is diced into a plurality of individual devices with a hermetic cavity over the microstructure. The applicable fields include micro-electronic circuits, micro-vibration systems, micro electrical-mechanical systems (MEMS), and gas discharge apparatuses.Type: ApplicationFiled: May 24, 2007Publication date: August 14, 2008Inventor: Chon-Ming Tsai
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Patent number: 7408250Abstract: A microstructure is packaged with a device substrate of the microstructure being attached to a package substrate. For dissipating possible deformation of the microstructure, which may result in device failure or quality degradation of the microstructure, an adhesive material comprising a compliant adhesive component is applied and positioned between the device substrate and package substrate.Type: GrantFiled: April 5, 2005Date of Patent: August 5, 2008Assignee: Texas Instruments IncorporatedInventors: Jonathan Doan, Terry Tarn
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Publication number: 20080067655Abstract: This invention discloses a process for manufacturing a device (44) comprising a packaged microsystem (10?): the device manufactured according to the invention is in the form of a plane wafer, the microsystem (10?) being buried in the wafer. Therefore, the process according to the invention is used to make a compound that may be used as a basis for other micro technology processes. Moreover, the process according to the invention co-integrates electronic compounds (36, 38) when the device (44) is being manufactured. The device (44) according to the invention is particularly suitable for MEMS, and particularly radiofrequency resonators.Type: ApplicationFiled: August 10, 2005Publication date: March 20, 2008Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Charlotte Gillot, Nicolas Sillon, Emmanuelle Lagoutte
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Patent number: 7342263Abstract: A circuit device is provided which can be manufactured at reduced costs and which is highly reliable. The circuit device includes a Sensor area formed on part of a semiconductor substrate, a circuit area formed around the sensor area on the semiconductor substrate to process electric signals produced at the sensor area, and a sealring disposed between the sensor area and the circuit area. The sealring is disposed between the outer periphery of the sensor area and the inner periphery of the circuit area to surround the sensor area. In the circuit device, the sealring prevents water or moisture from infiltrating from the sensor area into the circuit area.Type: GrantFiled: March 14, 2005Date of Patent: March 11, 2008Assignee: Sanyo Electric Co., Ltd.Inventor: Naoteru Matubara
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Patent number: 7301224Abstract: A surface acoustic wave device has a SAW device element 10 and a package 20 housing the SAW device element. The package includes a resin substrate 20 having metal patterns 21 and 22 formed on both surfaces thereof, and a resin cap 32. The SAW device element is mounted on one of the metal patterns of the resin substrate. The resin cap is adhered to the resin substrate to cover the SAW device element. The surfaces of the resin substrate are flush with corresponding end surfaces of the resin cap.Type: GrantFiled: August 29, 2005Date of Patent: November 27, 2007Assignee: Fujitsu Media Devices LimitedInventors: Naoyuki Mishima, Takumi Kooriike
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Patent number: 7274095Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.Type: GrantFiled: June 8, 2004Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventors: Setho Sing Fee, Lim Thiam Chye, Steven W. Heppler, Leng Nam Yin, Keith Tan, Patrick Guay, Edmund Lua Koon Tian, Yap Kah Eng, Eric Tan Swee Seng
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Publication number: 20070216021Abstract: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing a semiconductor device into a mold and subjecting a curable silicone composition that fills the spaces between said mold and said semiconductor device to compression molding, wherein the curable silicone composition comprises the following components: (A) an organopolysiloxane having at least two alkenyl groups per molecule; (B) an organopolysiloxane having at least two silicon-bonded hydrogen atoms per molecule; (C) a platinum-type catalyst; and (D) a filler, wherein either at least one of components (A) and (B) contains a T-unit siloxane and/or Q-unit siloxane. By the utilization this method, a sealed semiconductor device is free of voids in the sealing material, and a thickness of the cured silicone body can be controlled.Type: ApplicationFiled: December 7, 2004Publication date: September 20, 2007Applicant: DOW CORNING TORAY COMPANY LTD.Inventors: Yoshitsugu Morita, Katsutoshi Mine, Junji Nakanishi, Hiroji Enami
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Publication number: 20070090514Abstract: A semiconductor structure (100) includes a substrate (110) having a first surface (111) with a mold lock feature (101). The semiconductor structure also includes a semiconductor chip (120) located over the first surface of the substrate. The semiconductor structure further includes an electrical isolator structure (340) located over the first surface of the substrate. The electrical isolator structure includes an electrical lead (341, 342) and an electrically insulative element (343) molded to the electrical lead. An optional portion (444) of the electrical isolator structure is located in the mold lock feature. The semiconductor structure additionally includes an adhesive element (450) located between and coupling the electrical isolator structure and the first surface of the substrate.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Brian Condie, Lakshminarayan Viswanathan, Richard Wetz
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Publication number: 20070090515Abstract: A semiconductor structure (100, 900) includes a substrate (110) having a surface (111) and also includes one or more semiconductor chips (120) located over the substrate surface. The semiconductor structure further includes an electrical isolator structure (340) located over the substrate surface, where the electrical isolator structure includes one or more electrical leads (341, 342) and an organic-based element (343) molded to the electrical leads. The semiconductor structure also includes a solder element (350) coupling together the electrical isolator structure and the substrate surface.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Brian Condie, Lakshminarayan Viswanathan, Richard Wetz
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Patent number: 7166911Abstract: A MEMS inertial sensor is secured within a premolded-type package formed, at least in part, from a low moisture permeable molding material. Consequently, such a motion detector should be capable of being produced more economically than those using ceramic packages. To those ends, the package has at least one wall (having a low moisture permeability) extending from a leadframe to form a cavity, and an isolator (with a top surface) within the cavity. The MEMS inertial sensor has a movable structure suspended above a substrate having a bottom surface. The substrate bottom surface is secured to the isolator top surface at a contact area. In illustrative embodiments, the contact area is less than the surface area of the bottom surface of the substrate. Accordingly, the isolator forms a space between at least a portion of the bottom substrate surface and the package. This space thus is free of the isolator.Type: GrantFiled: September 28, 2004Date of Patent: January 23, 2007Assignee: Analog Devices, Inc.Inventors: Maurice S. Karpman, Nicole Hablutzel, Peter W. Farrell, Michael W. Judy, Lawrence E. Felton, Lewis Long