Abstract: An electronic device includes a semiconductor memory comprising column lines, row lines crossing the column lines, memory cells located at intersections between the column lines and the row lines, dummy insulating patterns located adjacent to the memory cells, liner layers formed on sidewalls of the memory cells, and dummy liner layers formed on sidewalls of the dummy insulating patterns.

Abstract: A self-aligned memory device includes a conductive bottom plug disposed within an insulating layer and having a coplanar top surface, a self-aligned planar bottom electrode disposed upon the coplanar top surface and having a thickness within a range of 50 Angstroms to 200 Angstroms, a planar switching material layer disposed upon the self-aligned planar bottom electrode, a planar active metal material layer disposed upon the planar switching material layer and a planar top electrode disposed above the planar active metal material layer, wherein the self-aligned planar bottom electrode, the planar switching material layer, the planar active metal material layer, and the planar top electrode form a pillar-like structure above the insulating layer.

Abstract: A semiconductor memory device includes a substrate, a first conductor layer, and a first insulator layer. The substrate includes a first region on which memory cells are provided, a second region on which a control circuit of the memory cells is provided, and a third region separating the first region and the second region. The first conductor layer is above the second region of the substrate. The first insulator layer is above the second and third regions of the substrate. The first insulator layer includes a first portion that is above the first conductor layer and extends along a surface direction of the substrate, and a second portion that is continuous with the first portion and extends along a thickness direction of the substrate from the first portion toward a surface of the substrate in the third region.

Abstract: A conductive bridge random access memory and its manufacturing method are provided. The conductive bridge random access memory includes a bottom electrode, an inter-metal dielectric, a resistance switching assembly, and a top electrode. The bottom electrode is disposed on a substrate, and the inter-metal dielectric is disposed above the bottom electrode. The resistance switching assembly is disposed on the bottom electrode and positioned in the inter-metal dielectric. The resistance switching assembly has a reverse T-shape cross-section. The top electrode is disposed on the resistance switching assembly and the inter-metal dielectric.

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating signature information with the client configurable logic for various purposes.

Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector element coupled in series. The MTJ memory element includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic reference layer structure includes one or more magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The two-terminal selector element includes a first inert electrode and a second inert electrode with a volatile switching layer interposed therebetween; a first active electrode formed adjacent to the first inert electrode; and a second active electrode formed adjacent to the second inert electrode. The volatile switching layer includes at least one conductor layer interleaved with insulating layers.

Abstract: A 3D memory includes a plurality of first access line levels, a plurality of second access line levels and a plurality of memory cell levels, the memory cell levels being disposed between corresponding first access line levels and second access line levels. The first access line levels include a plurality of first access lines extending in a first direction, and a plurality of remnants of a first sacrificial material disposed between the first access lines. The second access line levels include a plurality of second access lines extending in a second direction and a plurality of remnants of a second sacrificial material disposed between the second access lines. The memory cell levels include an array of memory pillars disposed in the cross-points between the first access lines and the second access lines in adjacent first and second access line levels.

Abstract: A metal liner is deposited conformally to a pore within a first dielectric material of a semiconductor device. The pore extends through the first dielectric material to a top surface of a first metal electrode. The metal liner is etched such that the metal liner only substantially remains on sidewalls of the pore. A phase change material is selectively deposited within the pore of the first dielectric layer to substantially fill the pore with the phase change material. The selective deposition of the phase change material produces a growth rate of phase change material on the metal liner at a substantially greater rate than a growth rate of the phase change material on exposed surfaces of the first dielectric material.

Abstract: A financial account system includes a stored-value card, a first financial account directly accessible via the stored-value card and a second financial account associated with the first financial account. Funds may be transferred between the first and the second financial account. The transfers between the first and the second financial account may be automatic, recurring, or one-time events and wherein the automatic, recurring, or one-time events may be transacted regardless of a current balance of the first financial account and/or the second financial account. The balances associated with the first and/or the second financial accounts may be used to collateralize loans.

Abstract: Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector element coupled in series. The MTJ memory element includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic reference layer structure includes one or more magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The two-terminal selector element includes a first inert electrode and a second inert electrode with a volatile switching layer interposed therebetween; a first active electrode formed adjacent to the first inert electrode; and a second active electrode formed adjacent to the second inert electrode. The volatile switching layer includes a plurality of metal-rich particles or clusters embedded in a matrix or at least one conductor layer interleaved with insulating layers.

Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element, which has a low resistance state and a high resistance state, and a two-terminal selector coupled to the MTJ memory element in series. The MTJ memory element includes a magnetic free layer and a magnetic reference layer with an insulating tunnel junction layer interposed therebetween. The two-terminal selector has an insulative state and a conductive state. The two-terminal selector in the conductive state has substantially lower resistance when switching the MTJ memory element from the low to high resistance state than from the high to low resistance state. The voltages applied to the memory cell to respectively switch the MTJ memory element from the low to high resistance state and from the high to low resistance state may be substantially same.

Abstract: In various examples, dual resistive-material regions for a phase change material region are fabricated by initially forming a resistive material. Prior to forming the phase change material region over the resistive material, at least an upper portion of the resistive material is exposed to an implantation or plasma that increases the resistance of an upper portion of the resistive material relative to the remainder, or bulk, of the resistive material. As a result, in certain embodiments, the portion of the resistive material proximate to the phase change material region may be used as a heater because of a relatively, high resistance value of the resistive material, but the bulk of the resistive material has a relatively lower resistance value and, thus, does not increase the voltage drop and current usage of the device. Other methods and devices are disclosed.

Abstract: Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. Resistance-increasing material is adjacent to and coextensive with the access/sense lines of one of the first and second series, and is between the adjacent access/sense lines and programmable material of the memory cells. Some embodiments include methods of forming memory arrays.

Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

Abstract: A resistive random access memory (RRAM) including a first electrode, a second electrode, and a charge trapping layer is provided. The second electrode is located on the first electrode. The charge trapping layer is located between the first electrode and the second electrode. The charge trapping includes a first region and a second region. The first region has a first dopant and is close to the first electrode. The second region has a second dopant and is close to the second electrode.

Abstract: A method for forming a semiconductor device includes incorporating chalcogen dopant atoms into a semiconductor doping region of a semiconductor substrate of a semiconductor device. The method further includes incorporating heavy metal atoms into the semiconductor doping region.

Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.

Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.

Abstract: Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

Abstract: According to one embodiment, a memory device includes a superlattice structure portion containing first chalcogen-compound layers and second chalcogen-compound layers differing in composition from the first chalcogen-compound layers are alternately deposited, a first layer provided on one of main surfaces of the superlattice structure portion in a deposition direction thereof, which has a larger energy gap than that of the superlattice structure portion, and a second layer provided on the other main surface of the superlattice structure portion in the deposition direction, which has a larger energy gap than that of the superlattice structure portion.

Abstract: According to one embodiment, a memory includes a resistance change layer includes a first chalcogenide layer, and a second chalcogenide layer having a composition different from that of the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and a semiconductor layer of a first conductivity type provided on a one of main surfaces of the resistance change layer.

Abstract: Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory as well as minimize electromigration, in accordance with embodiments. In one embodiment, a memory cell includes a first electrode and a second electrode, and a storage element comprising a layer of doped phase change material between the first and second electrodes, wherein the doped phase change material includes one or more of aluminum, zirconium, hafnium, and silicon. The storage element, a selector element, or both can be doped using techniques such as cosputtering or deposition of alternating layers of a dopant layer and a storage (or selector) material.

Abstract: A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines, where the second stratum includes a first layer including first transistors and a second layer including second transistors, where the first layer includes a first bus, the first bus interconnecting a plurality of first logic units, where the second layer includes a second bus, the second bus interconnecting a plurality of second logic units.

Abstract: Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.

Abstract: An antifuse-type OTP memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers the surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The second gate is connected with an antifuse control line. A third gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The third gate is connected with an isolation control line.

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the device includes a Phase Lock Loop (“PLL”) circuit, where the second clock distribution structure is connected to the Phase Lock Loop (“PLL”) circuit, and where the second transistors are aligned to the first transistors with less than 200 nm alignment error.

Abstract: A phase change memory (“PCM”) cell is provided in accordance with some embodiments. The PCM includes a spacer defining a reaction area; a phase change material layer disposed within the reaction area; a protection layer disposed over the phase change material layer and within the reaction area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.

Abstract: The invention provides a power semiconductor device and a method of fabricating the same and a cutoff ring. A cutoff ring located at a periphery of an active area of the power semiconductor device is etched forming at least one trench below which an implant area is formed by implanting ions into the trench, and a silicon dioxide dielectric layer covering the trench and a surface of the active area, are formed. Since the ions are implanted into the trench formed by etching the cutoff ring to thereby increase a depth of the implanted ions and a density of the cutoff ring, a width of the cutoff ring can be shortened to thereby address the technical problem of a considerable area of a chip occupied by the cutoff ring and improve a utilization ratio of the area of the chip so as to lower a cost of fabricating the chip.

Abstract: An anti-fuse type OTP memory cell includes a first anti-fuse transistor having a first channel width, a first selection transistor sharing a first active region with the first anti-fuse transistor and having a second channel width that is greater than the first channel width, a second anti-fuse transistor sharing a program gate with the first anti-fuse transistor and having a third channel width, and a second selection transistor sharing a second active region with the second anti-fuse transistor and having a fourth channel width that is greater than the third channel width.

Abstract: Provided is an electronic device including a semiconductor memory unit. The semiconductor memory unit may include: a storage cell comprising a variable resistance element; a first selecting element coupled to one end of the storage cell and having a threshold voltage set to a first voltage; and a second selecting element coupled to the other end of the storage cell and having a threshold voltage set to a second voltage higher than the first voltage.

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the second clock distribution structure is connected to the first clock distribution structure with a plurality of through layer vias, and where the second transistors are aligned to the first transistors with less than 100 nm alignment error.

Abstract: A magnetic memory according to an embodiment includes: a plurality of memory cells, each memory cell including a first MTJ element and a first selection unit; a pair of a first and second bit lines provided to each column of the memory cells; a word line provided to each row of the memory cells; an equalizer circuit provided to each column of the memory cells, and to connect between the first and second bit lines; and a control circuit that sets the first and second bit lines connected to a selected memory cell to be a first and second potentials to conduct a write operation, and after the write operation, transmits a control signal to the equalizer circuit between the first and second bit lines to activate the equalizer circuit to equalize potentials of the first bit line and the second bit line, thereby bringing into floating states.

Abstract: An anti-fuse type OTP memory cell includes a first active region having a first program region with a first width and a first selection region with a second width that is greater than the first width, a second active region spaced apart from the first active region and having a second program region with a third width and a second selection region with a fourth width that is greater than the third width, a program gate intersecting the first program region and the second program region, a first selection gate intersecting the first selection region, and a second selection gate intersecting the second selection region.

Abstract: Embodiments relate to a method of forming a memory array, comprising: forming a collector layer; forming a plurality of collector regions in the collector layer; forming a plurality of base regions over the collector region; forming a plurality of emitter regions over the base regions; forming a plurality of memory elements over the emitter regions, wherein the collector regions, base regions and emitter regions form heterojunction bipolar transistors.

Abstract: A memory cell includes a first resistive switching device having a first terminal and a second terminal, a switching device having a first terminal and a second terminal, and an access device having a first access terminal and a second access terminal. The first access terminal is coupled to the first terminal of the first resistive switching device and the first terminal of the switching device.

Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

Abstract: A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.

Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, two-terminal memristor devices. In one aspect, a device (400) includes an active region (402) for controlling the flow of charge carriers between a first electrode (104) and a second electrode (106). The active region is disposed between the first electrode and the second electrode and includes a storage material. Excess mobile oxygen ions formed within the active region are stored in the storage material by applying a first voltage.

Abstract: A method for fabricating a variable resistance device includes: providing a first insulating layer having a first electrode; forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer; forming a sacrifice pattern over the first oxide layer; forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen; removing the sacrifice pattern; and forming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer.

Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.

Abstract: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A variable resistance memory device includes a plurality of column selection switches, a plurality of variable resistance memory cells configured to be stacked and selected by the plurality of column selection switches, and a bit line connected to the plurality of variable resistance memory cells. Each of the plurality of variable resistance memory cells includes an ovonic threshold switch (OTS) element selectively driven by a plurality of word lines arranged to be stacked and a variable resistor connected in parallel to the OTS element.