Abstract: Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.

Abstract: A room-temperature semiconductor maser, including a first matching network, a second matching network, a heterojunction-containing transistor, and a resonant network. The output end of the first matching network is connected to the drain of the heterojunction-containing transistor. The input end of the second matching network is connected to the source of the heterojunction-containing transistor. The gate of the heterojunction-containing transistor is connected to the resonant network. The pumped microwaves are fed into the input end of the first matching network.

Abstract: A radio-frequency module includes a substrate and a switch IC mounted on the substrate and including a common terminal and a plurality of selection terminals. The substrate includes ground electrodes disposed between the common terminal and the plurality of selection terminals in a plan view of the substrate.

Abstract: Semiconductor devices, such as a lateral HEMT, may display current flow between a plurality of interdigitated source fingers and drain fingers, and controlled by a common gate connection. An extended source finger contact may enable improved voltage control across the source fingers, even for large devices with many and/or lengthy source fingers. In this way, unwanted subthreshold operations and switching oscillations may be avoided by reliably maintaining a source voltage at a desired level, to thereby provide fast and reliable switching.

Abstract: According to an embodiment of a semiconductor device, the device includes: a plurality of device cells formed in a semiconductor substrate, each device cell including a transistor structure and a Schottky diode structure; and a superjunction structure that includes alternating regions of a first conductivity type and of a second conductivity type formed in the semiconductor substrate. For each transistor structure, a channel region of the transistor structure and a Schottky metal region of an adjacent one of the Schottky diode structures are interconnected by semiconductor material of the first conductivity type without interruption by any of the regions of the second conductivity type of the superjunction structure, the semiconductor material of the first conductivity type including one or more of the regions of the first conductivity type of the superjunction structure.

Abstract: The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device.

Abstract: A semiconductor device or circuit includes a vertical bipolar junction transistor (vBJT) and a vertical filed effect transistor (vFET). The vBJT collector is electrically and/or physically connected to an adjacent vFET source. For example, a vBJT collector and a vFET source may be integrated upon a same semiconductor material substrate or layer. The vFET provides negative feedback for the collector-base voltage and the vBJT emitter and collector allow for low transit times.

Abstract: A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.

Abstract: A semiconductor device includes a substrate, a first III-V compound layer, a gate electrode, drain trenches, and at least one drain electrode. The drain trenches are disposed and arranged with high integrity. The substrate has a first side and a second side opposite to the first side. The first III-V compound layer is disposed at the first side of the substrate. The gate electrode is disposed on the first III-V compound layer. Each of the drain trenches extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trenches are arranged regularly. The drain electrode is disposed in at least one of the drain trenches.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, a first gate electrode, a second gate electrode, a first control transistor part, a gate interconnect, and a control gate interconnect. The semiconductor member includes first and second semiconductor layers. The semiconductor member includes first and second regions, and a first control region. The first and second gate electrodes extend along a first direction. A direction from the first region toward at least a portion of the first gate electrode is along a second direction crossing the first direction. The first control transistor part includes a first control gate electrode and a first control drain electrode. The first control drain electrode is electrically connected to the first and second gate electrodes. The gate interconnect is electrically connected to the first and second gate electrodes. The control gate interconnect is electrically connected to the first control gate electrode.

Abstract: According to an embodiment of the disclosure, a series or source feedback is provided to a solid-state power amplifier to achieve improved amplifier output power, good impedance match, and low voltage standing wave ratio (VSWR). In an embodiment, an inductive element is coupled to the source of the power amplifier transistor to serve as a series or source feedback for the transistor. In an embodiment, a high-impedance transmission line such as a microstrip or coplanar waveguide is provided as an inductive element coupled to the source of the transistor. In an embodiment, a series or source feedback is provided to each amplifier in a multistage amplifier circuit.

Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface facing each other in a thickness direction, the first main surface including a trench. The trench has a predetermined depth in the thickness direction and has a substantially wedge shape that has a first side surface and a second side surface that face each other and are not parallel to each other, and a first end surface and a second end surface that face each other and are substantially parallel to each other. The first side surface and the second side surface intersect each other at a line, or extension surfaces of the first side surface and the second side surface extended in the thickness direction intersect each other at a line, and the line extends in a first direction that does not align with a cleavage plane of the semiconductor substrate.

Abstract: An amplifier includes: a first transistor chip including a plurality of cells and provided beside an input matching substrate; a second transistor chip including a plurality of cells and provided beside the input matching substrate; a plurality of first bonding wires connecting the input matching substrate and the first transistor chip; and a plurality of second bonding wires connecting the input matching substrate and the second transistor chip, and variance of the mutual inductance of the first bonding wires and the second bonding wires is compensated by adjusting the self-inductance of the first bonding wires and the second bonding wires.

Abstract: Tracking movement of a lead vehicle and following vehicles driving to a common destination to maintain a specific relationship of the lead vehicle with the following vehicle(s) traveling through traffic conditions or obstacles such as traffic lights, intersections with stop signs, merging onto other roads, and other traffic obstacles such as road construction on the route to the common destination. The specific relationship is maintained by using data regarding the following vehicles of: real-time speed of the following vehicle, the following vehicle's current location, distance from the following vehicle to the lead vehicles, presence of other vehicles between the lead vehicle and following vehicle, and presence of other vehicles in adjacent lanes to the following vehicle.

Abstract: An in-phase (I) and quadrature (Q) demodulator includes an input for receiving a signal, a reference frequency source, and a sampler connected with the input. The sampler includes a sampler strobe connected with the reference frequency source, and a non-linear transmission line (NLTL) connected with the sampler strobe. The NLTL receives a strobe signal generated by the sampler strobe and multiplies a frequency of the strobe signal to generate a sampler signal. When the sampler receives a signal from the input, the sampler is configured to generate and output an intermediate frequency (IF) signal using the sampler signal. A splitter of the demodulator separates the IF signal into an in-phase (I) component and a quadrature (Q) component. Mixers receive the I and Q components and generate I and Q output signals shifted 90° in phase.

Abstract: Single stage ramped power amplifiers in accordance with embodiments of the invention are disclosed. In one embodiment, a single stage ramped power amplifier includes a RF transceiver, a ramp voltage, a power supply, and an output circuit, wherein the ramp voltage is coupled to a resistor that is coupled to a first inductor, the power supply is coupled to a second inductor, the RF transceiver is coupled to the second inductor and a first capacitor, the first capacitor is coupled to a PIN diode, the PIN diode is coupled to the first inductor and a second capacitor, the second capacitor is coupled to a first transistor, the first transistor is coupled to a third capacitor, the third capacitor is coupled to a third inductor, the third inductor is coupled to a second transistor, and the second transistor is coupled to the output circuit.

Abstract: A semiconductor device is provided with one or more gate fingers (20) that are provided in an active region on a semiconductor substrate (1), and a source finger (30) and a drain finger (40) that are provided in the active region and arranged alternately to allow each gate finger to be sandwiched between the source and drain fingers. The semiconductor device includes terminal circuit (60) that has inductive impedance at the frequency of a signal input to an input terminal of the one or more gate fingers, and is directly or indirectly connected to the one or more gate fingers at an area being spaced away from a connecting position of the input terminal (21a) of the one or more gate fingers (20).

Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

Abstract: The present disclosure provides for a phase shifter having at least one phase shift section. The phase shift section includes an input port for receiving an incoming radio frequency signal, an output port for transmitting an outgoing radio frequency signal, an input junction coupled to the input port, an output junction coupled to the output port, and a plurality of transmission lines. The input junction includes a first plurality of cantilever type switches, and the output junction includes a second plurality of cantilever type switches. Each transmission line connects one of the first plurality of cantilever type switches to a corresponding one of the second plurality of cantilever type switches. The first plurality of cantilever type switches, the second plurality of cantilever type switches, and the plurality of transmission lines are formed in a coplanar waveguide.

Abstract: A modular power amplifier system and an electronic device comprising the modular power amplifier system in which, the modular power amplifier system comprises a plurality of amplifier modules. The plurality of amplifier modules are arranged into a number of sections comprising a first section which comprises a first amplifier module configured to receive the input signal within a first amplitude range and provide an output signal having a first output power; a second section which comprises a second amplifier module configured to receive the input signal within a second amplitude range and provide an output signal having a second output power; and an i-th section which comprises multiple amplifier modules, each being configured to receive the input signal within a certain amplitude range and provide an output signal having a certain output power. The output signals of the amplifier modules are combined to provide output signals with scalable output power.

Abstract: Switching devices are provided. The switching devices include an input electrode, having a main electrode and a trigger electrode, and an output electrode. The main electrode and the trigger electrode are separated from the output electrode by a main gap and a trigger gap, respectively. During operation, the trigger electrode compresses and amplifies a trigger voltage signal causing the trigger electrode to emit a pulse of energy. This pulse of energy form plasma near the trigger electrode, either by arcing across the trigger gap, or by arcing from the trigger electrode to the main electrode. This plasma decreases the breakdown voltage of the main gap. Simultaneously, or near simultaneously, a main voltage signal propagates through the main electrode. The main voltage signal emits a main pulse of energy that arcs across the main gap while the plasma formed by the trigger pulse is still present.

Abstract: A cascode transistor circuit having an active region, the active region having a source, a drain, a floating source/drain, a first gate disposed between the source and the floating source/drain and a second gate disposed between the floating source/drain and the drain. A first gate pad is displaced from the active region and is electrically connected to the first gate and a second gate pad is displaced from the active region and is electrically connected to the second gate. The first and the second gate pads are disposed on opposite sides of the active region.

Abstract: Circuits and methods related to power amplifier efficiency based on multi-harmonic approximation. In some embodiments, an output network circuit can be provided for multi-harmonic control of a radio-frequency (RF) power amplifier. The output network circuit can include an impedance matching network configured for a fundamental frequency of the power amplifier. The output network circuit can further include a broadband harmonic trap in communication with the impedance matching network. The broadband harmonic trap can be configured to substantially trap a plurality of harmonics associated with the fundamental frequency. The output network circuit can further include a dipole network in communication with the broadband harmonic trap. The dipole network can be configured to tune reactances resulting from the operation of the broadband harmonic trap.

Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.

Abstract: The present invention relates to the field of a light emitting device (1), comprising a light emitting diode (2) arranged on a submount (3), said device having a lateral circumference surface (6) and a top surface (8), and an optically active coating layer (7), said coating layer (7): covering along at least a part of said circumference surface (6), extending from the submount (3) to said top surface (8), and essentially not covering the top surface (8). A method for producing the device is also disclosed.

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract: An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device.

Abstract: The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

Abstract: An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package.

Abstract: To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 1.91 eV or more.

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract: In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.

Abstract: According to one embodiment, a semiconductor device having a semiconductor substrate, first to fourth semiconductor layers of nitride, first to third electrodes and a gate electrode is provided. The first semiconductor layer is provided directly on the semiconductor substrate or on the same via a buffer layer. The second semiconductor layer is provided so as to be spaced apart from the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer and has a band gap wider than that of the second semiconductor layer. The fourth semiconductor layer insulates the first and second semiconductor layers. The first electrode forms an ohmic junction with the first to the third semiconductor layers. The second electrode is provided on the third semiconductor layer. The gate electrode is provided between the first and the second electrodes. The third electrode forms a Schottky junction with the first semiconductor layer.

Abstract: A III-nitride power semiconductor device that includes a first III-nitride power semiconductor device and a second III-nitride power semiconductor device formed in a common semiconductor die and operatively integrated to form a half-bridge.

Abstract: Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the III-nitride material region(s) may be essentially eliminated. The presence of a strain-absorbing layer underlying the III-nitride material region(s) and/or processing conditions can contribute to achieving the low screw dislocation densities. In some embodiments, the III-nitride material region(s) having low dislocation densities include a gallium nitride material region which functions as the active region of the device. The low screw dislocation densities of the active device region (e.g., gallium nitride material region) can lead to improved properties (e.g.

Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 102 microns per hour.

Abstract: A shaped article comprising a plurality of semiconductor nanocrystals. Devices incorporating shaped articles are also provided. Methods of manufacturing shaped articles by various molding processes are also provided.

Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.

Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.

Abstract: Disclosed is a monolithically integrated silicon and group III-V device that includes a group III-V transistor formed in a III-V semiconductor body disposed over a silicon substrate. At least one via extends through the III-V semiconductor body to couple at least one terminal of the group III-V transistor to a silicon device formed in the silicon substrate. The silicon device can be a Schottky diode, and the group III-V transistor can be a GaN HEMT. In one embodiment an anode of the Schottky diode is formed in the silicon substrate. In another embodiment, the anode of the Schottky diode is formed in a lightly doped epitaxial silicon layer atop the silicon substrate. In one embodiment a parallel combination of the Schottky diode and the group III-V transistor is formed, while in another embodiment is series combination is formed.

Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

Abstract: An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm?2 and at most 1×106 cm?2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.

Abstract: An optoelectronics chip-to-chip interconnects system is provided, including at least one packaged chip to be connected on the printed-circuit-board with at least one other packaged chip, optical-electrical (O-E) conversion mean, waveguide-board, and (PCB). Single to multiple chips interconnects can be interconnected provided using the technique disclosed in this invention. The packaged chip includes semiconductor die and its package based on the ball-grid array or chip-scale-package. The O-E board includes the optoelectronics components and multiple electrical contacts on both sides of the O-E substrate. The waveguide board includes the electrical conductor transferring the signal from O-E board to PCB and the flex optical waveguide easily stackable onto the PCB to guide optical signal from one chip-to-other chip. Alternatively, the electrode can be directly connected to the PCB instead of including in the waveguide board. The chip-to-chip interconnections system is pin-free and compatible with the PCB.

Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.

Abstract: The present invention relates to a process for fabricating integrated circuit system. More particularly, the process allows for fabrication of highly integrated system-on-a-chip modules through heterogeneous integration of different semiconductor technologies wherein alignment targets on the base semiconductor are used for precise lateral positioning of device structures above.

Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.

Abstract: A semiconductor light emitting device includes a multi-layered semiconductor layer having at least a first conductive type cladding layer, an active layer, a second conductive type first cladding layer, an etching stop layer, and a second conductive type second cladding layer on a substrate. An upper section of a ridge groove is formed by an anisotropic etching process, as a first groove in such a way as to have a depth from a surface of the multi-layered semiconductor layer and as not to cross the etching stop layer at the depth. A bottom groove of the ridge groove is formed by an isotropic etching process, as a second groove by performing etching in such a way as to be stopped by the etching stop layer.

Abstract: When to-be-detected light is made incident from a support substrate 2 side of a photocathode E1, a light absorbing layer 3 absorbs this to-be-detected light and produces photoelectrons. However, depending on the thickness and the like of the light absorbing layer 3, the to-be-detected light can be transmitted through the light absorbing layer 3 without being sufficiently absorbed by the light absorbing layer 3. The to-be-detected light transmitted through the light absorbing layer 3 reaches an electron emitting layer 4. A part of the to-be-detected light that has reached the electron emitting layer 4 proceeds toward a through-hole 5a of a contact layer 5. Since the length d1 of a diagonal line of the through-hole 5a is shorter than the wavelength of the to-be-detected light, the to-be-detected light can be suppressed from passing through the through-hole 5a and being emitted to the exterior.