Abstract: A sensor device coupled to a communication interface bus, the sensor device enters a low power mode in which some operations of the sensor device are suspended when the sensor device receives insufficient power over the bus, thereby significantly reducing the likelihood that digital components of the sensor device will need to be reset due to an under-voltage condition.

Abstract: According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrically coupled to each other, wherein the second set of transistors is configured to provide one or more output signals of the circuit, wherein the first set of transistors and the second set of transistors are electrically coupled to each other, and wherein, for each transistor of the first set of transistors and the second set of transistors, the transistor is configured to drive a load associated with the transistor and has an aspect ratio that is sized larger than an aspect ratio of a transistor that is optimized for driving the load.

Abstract: A memory device includes a plurality of data input/output (I/O) groups each including data I/O circuits, each data I/O circuit comprising a transistor having a predetermined threshold voltage according to a bulk voltage supplied to a bulk terminal thereof; a control circuit suitable for generating a control signal according to a data I/O mode; and a plurality of voltage supply circuits suitable for independently supplying bulk voltages to the plurality of data I/O groups, and changing, in response to the control signal, a level of a bulk voltage corresponding to data I/O groups unused in the data I/O mode, among the plurality of data I/O groups.

Abstract: Embodiments of the invention provide for a drop-in solid-state relay replacement for current standard relays. The drop-in solid-state relay may comprise receiving an input power and actuating at least one transistor to provide power to operational equipment. In some embodiments, an optical isolator may be disposed at an output driver stage of the relay circuit to provide electrical isolation between the input stage and the output stage. The drop-in solid-state relay may provide low input voltage, low heat, no noise, and not produce fly-back.

Abstract: There is provided a design support apparatus including a memory, and a processor coupled to the memory and the processor configured to obtain an arrangement target cell, and arrange the arrangement target cell at a position satisfying a condition of an arrangement position recommended for each cell when the arrangement target cell is arranged, based on definition information for defining the condition.

Abstract: An apparatus includes an integrated circuit, which includes a processor core, a plurality of input/output (I/O) circuits, and a plurality of over voltage tolerant (OVT) circuits. Each I/O circuit is associated with an I/O pad and is associated with an OVT circuit of the plurality of OVT circuits. At least one of the OVT circuits includes a passive circuit, which is adapted to receive a pad voltage from the associated I/O pad; receive a supply voltage of the associated I/O circuit; and based on a relationship of the received pad voltage relative to the received supply voltage, selectively couple a gate of a transistor of the associated I/O circuit to the pad voltage to inhibit a leakage current.

Abstract: A memory including current-limiting devices and methods of operating the same to prevent a spread of soft errors along rows in an array of memory cells in the memory are provided. In one embodiment, the method begins with providing a memory comprising an array of a plurality of memory cells arranged in rows and columns, wherein each of the columns is coupled to a supply voltage through one of a plurality of current-limiting devices, Next, each of the plurality of current-limiting devices are configured to limit current through each of the columns so that current through a memory cell in a row of the column due to a soft error rate event does not result in a lateral spread of soft errors to memory cells in the row in an adjacent column. Other embodiments are also provided.

Abstract: A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Abstract: A feedback path may be provided within the voltage regulator to reduce the effect of a current step or load transient on the output of a voltage regulator. The feedback path may provide a fast path for stabilizing the voltage regulator after the load transient. The feedback path may be configurable to be activated or de-activated during operation of the voltage regulator. The feedback path may be activated when the voltage regulator takes over generation of an output voltage from another voltage regulator. The feedback path may then be de-activated to allow normal operation of the voltage regulator after a steady-state condition is reached.

Abstract: A semiconductor device is provided, in which work of a parasitic bipolar transistor can be suppressed and a potential difference can be provided between a source region and a back gate region. A high voltage tolerant transistor formed over a semiconductor substrate includes: a well region of a first conductivity type; a first impurity region as the source region; and a second impurity region as a drain region. The semiconductor device further includes a third impurity region and a gate electrode for isolation. The third impurity region is formed, in planar view, between a pair of the first impurity regions, and from which a potential of the well region is extracted. The gate electrode for isolation is formed over the main surface between the first impurity region and the third impurity region.

Abstract: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.

Abstract: A vertical complementary field effect transistor (FET) relates to the production technology of semiconductor chips and more particularly to the production technology of power integration circuit. A part of the substrate bottom of the invention extends into the middle layer and form the plug between the two MOS units. There is an output terminal under the substrate layer. When on-state voltage is applied on the gate electrode of the two MOS units, two conduction paths are formed from MOS unit-plug-substrate to the output terminal. This technology can integrate more than two MOS devices. Therefore, the die size is reduced.

Abstract: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.

Abstract: The present invention discloses a coaxial transistor formed on a substrate, particularly a coaxial metal-oxide-semiconductor field-effect transistor (CMOSFET). The chips or substrates of the CMOSFETs can be stacked up and connected via through-holes to form a coaxial complementary metal-oxide-semiconductor field-effect transistor (CCMOSFET), which is both full-symmetric and full-complementarily, has a higher integration and is free of the latch-up problem.

Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).

Abstract: A semiconductor-on-insulator (SOI) substrate complementary metal oxide semiconductor (CMOS) device and fabrication methods include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). Each of the PFET and the NFET include a transistor body of a first type of material and source and drain regions. The source and drain regions have a second type of material such that an injection charge into the source and drain region is greater than a parasitic charge into the transistor body to decrease parasitic bipolar current gain, increase critical charge (Qcrit) and reduce sensitivity to soft errors.

Abstract: To provide a semiconductor integrated circuit including: a detection circuit that detects an occurrence of latch up and can be configured while adopting a layout configuration that suppresses the occurrence of latch up; and a recovery unit that enables a recovery from the latch up without cutting off a positive potential. The semiconductor integrated circuit includes: a n-channel MOS transistor 7 that is formed on a P-type region 3 on a semiconductor substrate; and a latch up detection circuit that detects an occurrence of latch up in the n-channel MOS transistor 7. The latch up detection circuit includes: a n-MOS transistor structure 12 in which a source 10 and a back gate 8 are connected in common with a source 5 and the back gate 8 of the n-channel MOS transistor 7; and an electric current detection unit 15 that detects an electric current flowing to a drain 9 of the n-MOS transistor structure 12.

Abstract: The present invention discloses a coaxial transistor formed on a substrate, particularly a coaxial metal-oxide-semiconductor field-effect transistor (CMOSFET). The chips or substrates of the CMOSFETs can be stacked up and connected via through-holes to form a coaxial complementary metal-oxide-semiconductor field-effect transistor (CCMOSFET), which is both full-symmetric and full-complementarily, has a higher integration and is free of the latch-up problem.

Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).

Abstract: In a first functional block, a source voltage input terminal of a PMOS transistor and a substrate voltage input terminal of an NMOS transistor are connected to their voltage supply terminals, respectively. The substrate voltage input terminal of the PMOS transistor in the ith (1?i?n?1) functional block and the source voltage input terminal of the NMOS transistor therein are connected bijectively with the source voltage input terminal of the PMOS transistor in the i+1th functional block and the substrate voltage input terminal of the NMOS transistor therein. In the nth functional block, the substrate voltage input terminal of the PMOS transistor and the source voltage input terminal of the NMOS transistor are connected to their voltage supply terminals, respectively.

Abstract: Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit, to reduce the base resistances (RP?, RP?) of the two bipolar transistors, at least one of the metallizations (16, 19) performed to reduce the base resistances (RN?, RP?) of the two bipolar transistors, being connected to a power supply metallization (15, 16) in the integrated circuit, entirely through the substrate (1, 2).

Abstract: A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.

Abstract: A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.

Abstract: A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.

Abstract: A photo mask and a semiconductor device fabricated using the same is disclosed. The photo mask to form a mask pattern defining a STAR gate region includes a transparent substrate, and a light-shielding pattern defining a zigzag W-STAR gate region, wherein a waved portion of the light-shielding pattern partially overlaps a gate region and a storage node contact region of an active region disposed on a semiconductor substrate. The semiconductor device includes an active region and a device isolation region defining the active region disposed in a semiconductor substrate, a gate electrode, wherein a line width of the gate electrode in the active region is greater than that in the device isolation region, and a zigzag W-STAR gate region, wherein the waved portion of the zigzag W-STAR gate region partially overlaps the gate region and the storage node contact region in the active region.

Abstract: A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.

Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

Abstract: A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a cond

Abstract: A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from accidentally turning on. In an intended application of the composite integrated circuit to a startup circuit of a switching-mode power supply, the multipurpose resistor serves as startup resistor for limiting the flow of rush current during the startup period of the switching-mode power supply.

Abstract: The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the <100> direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.

Abstract: A metal oxide semiconductor field effect transistor includes a semiconductor substrate; a well region containing an impurity of a first conductivity type disposed on the semiconductor substrate, the well region including a source region and a drain region formed by adding an impurity of a second conductivity type, the source region and the drain region being separated from each other by a predetermined gap; an insulating film disposed on the surface of the well region in the gap between the source region and the drain region; and a gate electrode disposed on the insulating film. The well region is composed of an epitaxial layer, and the epitaxial layer includes an impurity layer of the first conductivity type having a different impurity concentration.

Abstract: A structure for preventing leakage of a semiconductor device is provided. The structure comprises a shielding line, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The shielding line is wider than the conductive line.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a SRAM region; an N-type element region formed in the SRAM region on the semiconductor substrate and including N-type source/drain regions; a P-type element region formed in the SRAM region on the semiconductor substrate so as to be substantially parallel to the N-type element region and including P-type source/drain regions; P-type well contact connections and N-type well contact connections formed on both sides of the N-type and P-type element regions in a longitudinal direction outside the SRAM region on the semiconductor substrate, respectively; an element isolation region for isolating the N-type element region, the P-type element region, the P-type well contact connection and the N-type well contact connection; a P-type well continuously formed under the N-type element region and the P-type well contact connection in the semiconductor substrate, and an N-type well continuously formed under the P-type element re

Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. Numerous other aspects are provided.

Abstract: A system and method is disclosed for using a differential wet etch stop technique to provide a uniform oxide layer over a metal layer in a laser trimmed fuse. A layer of boron doped oxide with a slow etch rate is placed over the metal layer. A layer of phosphorus doped oxide with a fast etch rate is placed over the boron doped oxide. The time period required for a wet etch process to etch through the phosphorus doped oxide is calculated. The wet etch process is then applied to the phosphorus doped oxide for the calculated time period. The wet etch process slows significantly when it reaches the boron doped oxide. This method forms a uniform layer of boron doped oxide over the metal layer.

Abstract: A thin film transistor substrate having improved display quality includes a gate line, a data line intersecting the gate line and providing a pixel region adjacent the gate line and the data line, a data pattern formed on substantially a same plane and of substantially a same metal as the data line, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, an organic protective layer formed under the pixel electrode and protecting the thin film transistor, and an inorganic protective layer formed between the data pattern and the organic protective layer, the inorganic protective layer formed on the data pattern with a pattern similar to the data pattern. A manufacturing method of the above-described thin film transistor substrate is further provided.

Abstract: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.

Abstract: The present invention discloses a coaxial transistor formed on a substrate, particularly a coaxial metal-oxide-semiconductor field-effect transistor (CMOSFET). The chips or substrates of the CMOSFETs can be stacked up and connected via through-holes to form a coaxial complementary metal-oxide-semiconductor field-effect transistor (CCMOSFET), which is both full-symmetric and full-complementarily, has a higher integration and is free of the latch-up problem.

Abstract: In a complementary SiGe bipolar process, a pnpn thyristor structure is formed from some of the layers of a pnp transistor and an npn transistor formed on top of each other and making use of the SiGe gates to define the blocking junction.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p? substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

Abstract: Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: A method of fabricating an electrical structure with increased charge carrier mobility is provided. The method includes forming an N-type field effect transistor (nFET) device and a P-type field effect transistors (pFET) device on a semiconductor substrate; forming a compressive stress film over said nFET device for exerting tensile stress in a first channel associated with said nFET device; and forming a tensile stress film over said pFET device for exerting compressive stress in a second channel associated with said pFET. The method further includes forming at least one shallow region between a first gate associated with said nFET and a second gate associated with said pFET for generating conductive stresses in said first and second channels.