Abstract: A thin-film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a pair of metal TFR heads (e.g., copper damascene trench structures), a TFR element formed directly on the metal TFR heads to define a conductive path between the pair of TFR heads through the TFR element, and TFR contacts connected to the TFR heads. The TFR heads may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The TFR element may be formed by depositing and patterning a TFR element/diffusion barrier layer over the TFR heads and interconnect elements formed in the metal interconnect layer. The TFR element may be formed from a material that also provides a barrier against metal diffusion (e.g., copper diffusion) from each metal TFR head and interconnect element. For example, the TFR element may be formed from tantalum nitride (TaN).

Abstract: Described herein are concepts, system and techniques which provide a means to construct robust high-field superconducting magnets using simple fabrication techniques and modular components that scale well toward commercialization. The resulting magnet assembly—which utilizes non-insulated, high temperature superconducting tapes (HTS) and provides for optimized coolant pathways—is inherently strong structurally, which enables maximum utilization of the high magnetic fields available with HTS technology. In addition, the concepts described herein provide for control of quench-induced current distributions within the tape stack and surrounding superstructure to safely dissipate quench energy, while at the same time obtaining acceptable magnet charge time. The net result is a structurally and thermally robust, high-field magnet assembly that is passively protected against quench fault conditions.

Abstract: A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer.

Abstract: A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer.

Abstract: Capacitive energy storage devices (CESDs) are disclosed, along with methods of making and using the CESDs. A CESD includes an array of electrodes with spaces between the electrodes. A dielectric material occupies spaces between the electrodes; regions of the dielectric material located between adjacent electrodes define capacitive elements. The disclosed CESDs are useful as energy storage devices and/or memory storage devices.

Abstract: An LC composite device includes a capacitor portion, an inductor portion, and a magnetic body portion. The capacitor portion is configured of a first substrate and a thin film capacitance element formed on the first substrate through a thin film process. The inductor portion is configured of a second substrate and a thin film inductance element formed on the second substrate through a thin film process. The magnetic body portion includes a magnetic substrate, and the capacitor portion. The inductor portion and the magnetic body portion are stacked in a positional relationship in which the magnetic body portion and the inductor portion are in contact with each other.

Abstract: A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer.

Abstract: A thin-film capacitor includes a body in which a plurality of dielectric layers and first and second electrode layers are alternately stacked on a substrate, first and second electrode pads are on external surfaces of the body, and a plurality of vias are within the body. Among the plurality of vias, a first via connects the first electrode layer and the first electrode pad, and a second via connects the second electrode layer and the second electrode pad. The first via and the second via are units each include a plurality of vias, and the first via unit and the second via unit are alternately disposed on an upper surface of the body.

Abstract: A Magnetic Resonance Imaging (MRI) receiver includes a receiver coil on a substrate. The receiver coil includes one or more capacitors. The construction of the capacitors allows for the use of very flexible substrates and allows the capacitors themselves to be highly flexible. The increased flexibility permits the MRI receiver to be conformed to the body of a patient and accordingly improves the MRI process.

Abstract: A display panel includes input power supply line coupled to a power supply at one or more edge portions of the display panel, and an output power supply line coupled to the input power supply line at a predetermined portion of the display panel. The input power supply line receives the power supply voltage, and the output power supply line receives the power supply voltage from the input power supply line. The power supply is coupled to the output power supply line at the one or more edge portions of the display panel, and receives the power supply voltage from the output power supply line to adjust a voltage level of the power supply voltage based on the power supply voltage from the output power supply line. The predetermined portion is at a location different from an edge of the display panel.

Abstract: A Magnetic Resonance Imaging (MRI) receiver includes a receiver coil on a substrate. The receiver coil includes one or more capacitors. The construction of the capacitors allows for the use of very flexible substrates and allows the capacitors themselves to be highly flexible. The increased flexibility permits the MRI receiver to be conformed to the body of a patient and accordingly improves the MRI process.

Abstract: An electrical component is disclosed, the electrical component comprising: a magnetic body having a top surface, a bottom surface, wherein at least one first conductive through hole is formed from the top surface to bottom surface of the magnetic body; and a coil disposed in the magnetic body, wherein a first end of the coil is electrically connected to one of the at least one first conductive through hole.

Abstract: A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.

Abstract: An object is to provide a thin film transistor having favorable electric characteristics and a semiconductor device including the thin film transistor as a switching element. The thin film transistor includes a gate electrode formed over an insulating surface, a gate insulating film over the gate electrode, an oxide semiconductor film which overlaps with the gate electrode over the gate insulating film and which includes a layer where the concentration of one or a plurality of metals contained in the oxide semiconductor is higher than that in other regions, a pair of metal oxide films formed over the oxide semiconductor film and in contact with the layer, and a source electrode and a drain electrode in contact with the metal oxide films. The metal oxide films are formed by oxidation of a metal contained in the source electrode and the drain electrode.

Abstract: Provided are an organic light emitting display device and a method for manufacturing the same. The organic light emitting display device comprises a transistor on a substrate, a cathode on the transistor and connected to a source or a drain of the transistor, a bank layer on the cathode and having an opening, a metal buffer layer on the cathode, an organic light emitting layer on the metal buffer layer, and an anode on the organic light emitting layer.

Abstract: A thin film transistor including: an active layer formed on a substrate; a gate insulating layer pattern formed on a predetermined region of the active layer; a gate electrode formed on a predetermined region of the gate insulating layer pattern; an etching preventing layer pattern covering the gate insulating layer pattern and the gate electrode; and a source member and a drain member formed on the active layer and the etching preventing layer pattern.

Abstract: Provided is a semiconductor device including a metal dummy pattern and a thin film resistor. In detail, a semiconductor device includes a semiconductor substrate, a thin film resistor, and a metal dummy pattern. The thin film resistor disposed over the semiconductor substrate and extending in a first direction relative to the semiconductor substrate. The metal dummy pattern disposed between the semiconductor substrate and the thin film resistor, the metal dummy pattern including a reflective pattern extending in the first direction semiconductor substrate and spatially corresponding to a periphery of the thin film resistor.

Abstract: Provided is a method capable of forming a polycrystalline silicon resistor with preferable ratio accuracy so as to design a resistor circuit with high accuracy. In the method, a length of a low concentration impurity region constituting the polycrystalline silicon resistor in a longitudinal direction is varied in accordance with an occupying area of a metal portion overlapping the low concentration impurity region, thereby correcting a variation in resistance without varying an external shape and the occupying area of the resistor.

Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

Abstract: A pixel structure includes a substrate; a scan line; a gate electrode; an insulating layer disposed on the scan line, the gate electrode and the substrate; a channel and a data line disposed on the insulating layer; a source electrode and a drain electrode disposed on the channel; a passivation layer; a pixel electrode and a connecting electrode. The data line does not overlap the scan line. The passivation layer disposed on the source electrode and the drain electrode includes a first contact hole partially exposing the drain electrode, and a plurality of second contact holes partially exposing the data line or the scan line. The pixel electrode disposed on the passivation layer is electrically connected to the drain electrode through the first contact hole. Furthermore, the connecting electrode disposed on the passivation layer is electrically connected to the data line or the scan line through the second contact holes.

Abstract: A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. A third electrically conductive material layer is in contact with and positioned on the second electrically conductive material layer. The third electrically conductive material layer overhangs the second electrically conductive material layer.

Abstract: Electronic devices that use desiccants for protection from moisture. The electronic devices comprise a substrate (12) and an electronic organic element (22) disposed over the top surface of the substrate. The substrate has one or more voids (14) which store desiccants (24). The voids penetrate partially or completely through the thickness of the substrate. An environmental barrier (20) is disposed over the electronic organic element and the voids. Also provided are methods for making electronic devices that use desiccants.

Abstract: A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode.

Abstract: Provided is a semiconductor device including a metal dummy pattern and a thin film resistor. In detail, a semiconductor device includes a semiconductor substrate, a thin film resistor, and a metal dummy pattern. The thin film resistor disposed over the semiconductor substrate and extending in a first direction relative to the semiconductor substrate. The metal dummy pattern disposed between the semiconductor substrate and the thin film resistor, the metal dummy pattern including a reflective pattern extending in the first direction semiconductor substrate and spatially corresponding to a periphery of the thin film resistor.

Abstract: Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer.

Abstract: Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.

Abstract: To provide a semiconductor device having a function equivalent to that of IGFET, an activation layer is formed by a crystal silicon film crystallized by using a catalyst element helping promote crystallization and a heating treatment is carried out in an atmosphere including a halogen element by which the catalyst element is removed, the activation layer processed by such steps is constituted by a peculiar crystal structure and according to the crystal structure, a rate of incommensurate bonds in respect of all of bonds at grain boundaries is 5% or less (preferably, 3% or less).

Abstract: A thin film transistor (TFT), including a crystalline semiconductor pattern on a substrate, a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein, a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes, an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein, and source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes.

Abstract: It is an object of the present invention to manufacture a micromachine having a plurality of structural bodies with different functions and to shorten the time required for sacrifice layer etching in a process of manufacturing the micromachine. Another object of the present invention is to prevent a structural layer from being attached to a substrate after the sacrifice layer etching. In other words, an object of the present invention is to provide an inexpensive and high-value-added micromachine by improving throughput and yield. The sacrifice layer etching is conducted in multiple steps. In the multiple steps of the sacrifice layer etching, a part of the sacrifice layer that does not overlap with the structural layer is removed by the earlier sacrifice layer etching and a part of the sacrifice layer that is under the structural layer is removed by the later sacrifice layer etching.

Abstract: The present invention relates to a thin film transistor, a method thereof and an organic light emitting device including the thin film transistor. According to an embodiment of the present invention, the thin film transistor includes a substrate, a control electrode, an insulating layer, a first electrode and a second electrode, a first ohmic contact layer and a second ohmic contact layer, and a semiconductor layer. The control electrode is formed on the substrate, and the insulating layer is formed on the control electrode. The first and the second electrodes are formed on the insulating layer. The first ohmic contact layer and the second ohmic contact layer are formed on the first electrode and the second electrode. The semiconductor layer is formed on the first ohmic contact layer and the second ohmic contact layer to fill between the first and the second electrodes.

Abstract: Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).

Abstract: An organic light emitting device includes a transistor having gate, source, and drain electrodes, and first electrode connected to one of the source or drain electrodes. The device also includes an emitting layer positioned on the first electrode and a second electrode positioned on the emitting layer. Each of the source and drain electrodes includes first, second, and third layers having different tapered angles. The first electrode may include a metallic layer and a conductive layer, with a tapered angle of the metallic layer being different from a tapered angle of the conductive layer.

Abstract: A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: The electronic component includes a base material, a capacitor unit, and a wiring portion. The capacitor unit has a stacked structure including a first electrode portion provided on the base material, a second electrode portion including a first surface opposing the first electrode portion and a second surface opposite to the first surface, and a dielectric portion interposed between the electrode portions. The wiring portion includes a via portion having a surface on the base material side, and joined to the second surface of the second electrode portion via the surface on the base material side. The surface of the via portion on the base material side includes an extending portion extending outward of the periphery of the second surface of the second electrode portion.

Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.

Abstract: An electronic device and/or component is manufactured using additive processing steps, including additive printing steps. A first layer is printed using additive printing techniques wherein a single first material is used to print the first layer in a single processing step. A second layer is printed in more than a single printing step where a first portion of the second layer is printed using a second material and a second portion of the second layer is printed using a third material, and the second and third materials are different from each other.

Abstract: An anodic metal layer, e.g., a tantalum layer, is deposited. An anodization mask is formed, the anodization mask exposing first portions of the tantalum layer and covering second portion of the tantalum layer. The exposed first portions of the tantalum layer are anodized to form a tantalum pentoxide layer. The amount of the tantalum layer converted to the tantalum pentoxide layer is precisely controlled by the applied anodization potential. Accordingly, the thicknesses of the remaining tantalum layer and the formed tantalum pentoxide layer are precisely controlled allowing the values of passive devices, e.g., resistors and capacitors, formed with the tantalum layer and/or the tantalum pentoxide layer to be precisely set.

Abstract: A thin film panel is provided, which includes a first signal line and a second signal line crossing the first signal line and formed on a different layer from the first signal line. The second signal line includes an expansion having an enlarged area and at least one cutout, and is disposed adjacent to a crossing region where the second signal line crosses the first signal line.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, the source wires 126 of a pixel portion 205 are formed of material having low resistance (representatively, aluminum, silver, copper). The source wires of a driving circuit are formed in the same process as the gate wires 162 of the pixel portion and a pixel electrode 163.

Abstract: A flat panel display is disclosed. The flat panel display includes a display panel having a display area on which a plurality of pixels are formed, an inspection pad formed in a non-display area outside the display area of the display panel, an inspection switch formed in the non-display area, and an electrostatic protection circuit including a plurality of dummy thin film transistors (TFTs) whose gate electrodes are commonly connected to a signal line connecting the inspection pad to the inspection switch. The inspection pad contacts an external inspection device. The inspection switch applies an inspection signal received from the inspection pad to the pixels.

Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

Abstract: A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mask, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the first wire via the contact holes.

Abstract: An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and a second dielectric layer on the first dielectric layer and the bottom plate, and a thin film top plate disposed on the second dielectric layer. The thin film top plate and bottom plate are composed of thin film resistive layers, such as sichrome, which also are utilized to form back end thin film resistors having various properties. Interconnect conductors of a metallization layer contact the top and bottom plates through corresponding vias.

Abstract: An organic light emitting device includes a transistor having gate, source, and drain electrodes, and first electrode connected to one of the source or drain electrodes. The device also includes an emitting layer positioned on the first electrode and a second electrode positioned on the emitting layer. Each of the source and drain electrodes includes first, second, and third layers having different tapered angles. The first electrode may include a metallic layer and a conductive layer, with a tapered angle of the metallic layer being different from a tapered angle of the conductive layer.

Abstract: A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements.

Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.

Abstract: An organic light emitting device includes a transistor having gate, source, and drain electrodes, and first electrode connected to one of the source or drain electrodes. The device also includes an emitting layer positioned on the first electrode and a second electrode positioned on the emitting layer. Each of the source and drain electrodes includes first, second, and third layers having different tapered angles. The first electrode may include a metallic layer and a conductive layer, with a tapered angle of the metallic layer being different from a tapered angle of the conductive layer.

Abstract: Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).

Abstract: A capacitor array in an integrated circuit with active unit capacitor cells arranged amongst the dummy unit capacitor cells to provide visual and electrical symmetry. The electrical symmetry provides electrical matching between active unit capacitor cells and the visual symmetry provide process uniformity between the unit capacitor cells. Visual symmetry may be provided by uniform capacitor plate selection and uniform spacing between each. Electrical symmetry is provided by appropriately arranging active unit capacitors amongst dummy unit capacitors in the capacitor array. The capacitor array may be used in an integrated circuit such as for a equally weighted or binary weighted capacitor array or ladder in an analog to digital converter or a digital to analog converter. Methods and rules of layout for arranging the unit capacitors may be manually performed or automatically performed by computer aided design software.