Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

Abstract: A semiconductor device and an output circuit thereof for accelerating rising of a pull-up transistor are provided. The output circuit of the invention includes an external terminal (130), an output buffer (110) and a pre-buffer circuit (120). The external terminal (130) can output output data to an external part. The output buffer (110) is connected to the external terminal (130) and includes a pull-up transistor (Qp1) of P type and a pull-down transistor (Qn1) of N type. The pre-buffer circuit (120) outputs a pull-up signal (PU) and a pull-down signal (PD) corresponding to the output data to the output buffer (110). The pre-buffer circuit (120) also includes a circuit (122). The circuit (122) negatively boosts the pull-up signal (PU) when the pull-up signal (PU) is changed from a high level into a low level.

Abstract: A semiconductor device includes a semiconductor body with a base layer and a field shaping zone of a first conductivity type. The base layer extends parallel to a back surface of the semiconductor body in a central portion and into an edge portion that surrounds the central portion. The field shaping zone is formed in the edge portion and has a maximum dopant concentration exceeding at least three times a maximum dopant concentration in the base layer. A back side metal structure directly adjoins the back surface in the central portion and extends over the edge portion. A dielectric structure is between the back side metal structure and the field shaping zone. Leakage current mechanisms reducing the reverse blocking capabilities are reduced.

Abstract: GaN-based heterojunction field effect transistor (HFET) sensors are provided with engineered, functional surfaces that act as pseudo-gates, modifying the drain current upon analyte capture. In some embodiments, devices for sensing nitric oxide (NO) species in a NO-containing fluid are provided which comprise a semiconductor structure that includes a pair of separated GaN layers and an AlGaN layer interposed between and in contact with the GaN layers. Source and drain contact regions are formed on one of the GaN layers, and an exposed GaN gate region is formed between the source and drain contact regions for contact with the NO-containing fluid. The semiconductor structure most preferably is formed on a suitable substrate (e.g., SiC). An insulating layer may be provided so as to cover the semiconductor structure. The insulating layer will have a window formed therein so as to maintain exposure of the GaN gate region and thereby allow the gate region to contact the NO-containing fluid.

Abstract: A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technology. According to an example embodiment of the present invention, the semiconductor device includes a pass device having a channel in a fin portion over a semiconductor substrate, and a thyristor device coupled to the pass device. The fin has a top portion and a side portion and extends over the semiconductor substrate. The pass device includes source/drain regions separated by the channel and a gate facing and capacitively coupled to the side portion of the fin that includes the channel. The thyristor device includes anode and cathode end portions, each end portion having base and emitter regions, where one of the emitter regions is coupled to one of the source/drain regions of the pass device.

Abstract: A semiconductor device includes at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type, a first well region of a second conductivity type, a second well region of a first conductivity type, a drift region of a second conductivity type, a collector region of a first conductivity type, and a collector contact. Each cell is disposed within the first well region, and the first well region is disposed within the second well region. The device further includes a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region, and at least one embedded region embedded in the first well region. The device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first well region and the second well region.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: A cellular transistor includes an N-type heavily doped (N+) buried layer (NBL), an N-well connected to the NBL, an N+ layer connected to the N-well and multiple drains. The N-well is formed after formation of the NBL. The N+ layer is formed after formation of the N-well. The multiple drains are connected to the NBL via the N-well and the N+ layer.

Abstract: According to the invention there is provided a semiconductor device including: at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type; a first well region of a second conductivity type; a second well region of a first conductivity type; a drift region of a second conductivity type; a collector region of a first conductivity type; a collector contact; in which each cell is disposed within the first well region and the first well region is disposed within the second well region; the device further including: a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region; and at least one embedded region embedded in the first well region; in which the device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first well

Abstract: A method for integration is disclosed herein. The method includes forming an N-type double drain (NDD) layer, and fabricating at least one transistor from a controller circuitry and a transistor switch on a single chip. The controller circuitry is operable for controlling the transistor switch.

Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a silicon controlled rectifier (SCR) having at least one first type high dopant region coupled to a first reference potential of the protected circuitry, and at least one second type high dopant region coupled to a second reference potential of the IC. The SCR is triggered by an external on-chip trigger device, which is adapted for injecting a trigger current into at least one gate of the SCR.

Abstract: One aspect of this disclosure relates to a memory cell. Various memory cell embodiments include an isolated semiconductor region separated from a bulk semiconductor region, an access transistor and a vertically-oriented thyristor formed in a trench extending between the isolated and bulk semiconductor regions. The access transistor includes a first diffusion region connected to a bit line, a second diffusion region to function as a storage node, a floating body region, and a gate separated from the floating body region by a transistor gate insulator. The isolated semiconductor region includes the first and second diffusion regions and the floating body region of the access transistor. The thyristor has a first end in contact with the bulk semiconductor region and a second end in contact with the storage node. The thyristor is insulated from the floating body region by a thyristor gate insulator. Other aspects and embodiments are provided herein.

Abstract: A semiconductor power component having an anode contact on the reverse side, an emitter region of a first conductor type on the reverse side, which is connected to the anode contact on the reverse side, a drift zone which is connected to the emitter region that is on the reverse side and extends partially to the front surface, an MOS control structure on the front side, having a control contact positioned in insulated fashion, a cathode contact on a front side which is connected to a source region and a first body region. The drift zone has first and second drift region of a second conductor type and a third drift region of first conductor type. First drift region is a buried region, second drift region connects the front surface to first drift region, and third drift region connects the first and/or second body region to first drift region.