Abstract: A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38, 60). The small features of the buried regions (38, 60) are maintained as such by minimizing high temperature and long duration processing of the chip. An emitter (42, 86) is formed in the epitaxial layer (40, 84).

Abstract: A semiconductor apparatus is equipped with an internal circuit (201) including a semiconductor element (202)(203) and a protection circuit (101) including a semiconductor (102)(103) for protecting the internal circuit (201) against damage from electrostatic discharge (ESD). The semiconductor elements (102)(103) (202)(203) constituting the internal circuit (201) and the protection circuit (101) include an impurity diffusion region (7)(8) connected by an external terminal and a guard band region (6)(5) formed near the impurity diffusion region (7)(8), respectively. A shortest distance (102L)(103L) between the impurity diffusion region (7)(8) and the guard band region (6)(5) in the semiconductor element (102)(103) of the protection circuit (101) is set to be shorter than a shortest distance (202L)(203L) between the impurity diffusion region (7)(8) and the guard band region (6)(5) in the semiconductor element (202)(203) of the internal circuit (201).

Abstract: A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions.

Abstract: A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage without involving any external circuitry or terminal, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage without sacrificing the ESD protection robustness. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.

Abstract: A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38, 60). The small features of the buried regions (38, 60) are maintained as such by minimizing high temperature and long duration processing of the chip. An emitter (42, 86) is formed in the epitaxial layer (40, 84).

Abstract: The invention concerns at disc comprising a highly-doped substrate (20) of a first type of conductivity, a lightly-doped epitaxial layer (22) of the second type of conductivity including in the neighbourhood of the substrate (20) a more highly-doped part (21), a highly-doped region (24) of the first type of conductivity on the side of the upper surface of the epitaxial layer, a region (23) of the second type of conductivity more doped than the epitaxial layer beneath the region (24) of the first type of conductivity and not overlapping relative thereto, a channel retaining ring (25) of the second type of conductivity more highly doped than the epitaxial layer, outside the first region, a wall (26) of the first type of conductivity outside said ring, joining the substrate.

Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source. An n-type conductivity region is provided on the p-type conductivity region beneath the source region and extending toward the drain region without extending beyond the end of the p-type conductivity region. Related methods of fabricating MESFETS are also provided.