Asymmetrical Thyristor (epo) Patents (Class 257/E29.224)
  • Patent number: 8703547
    Abstract: The present invention provides a device for electrostatic discharge and the method of manufacturing thereof. P-well is formed on the substrate, and a first N+ doped region, a second N+ doped region and a P+ doped region are formed in the P-well; both ends of each doped region adopt shallow trench isolation for isolation. A lightly doped source-drain region portion is formed between the first N+ doped region and the shallow trench isolation connected thereto. Under the source-drain region, a halo injection with an inverse type is formed. The reverse conduction voltage of the collector of the bipolar transistor is lowered through the introduction of special doped region and the adoption of lightly doped source-drain technology for manufacturing the source-drain region as well as the manufacturing of halo injection with inverse type under the source-drain region, thus reducing the trigger voltage of the device.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: April 22, 2014
    Assignee: Grace Semiconductor Manufacturing Corporation
    Inventors: Yi Shan, Jun He
  • Patent number: 8598621
    Abstract: A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: December 3, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 8390124
    Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: March 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Naoya Inoue, Yoshihiro Hayashi, Kishou Kaneko