Abstract: The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).

Abstract: Provided is a semiconductor device with a diode and a silicon controlled rectifier (SCR) including a substrate having a first conductivity type, a well region having a second conductivity type, a first doped region having the first conductivity type, and a second doped region having the second conductivity type. The well region is disposed in the substrate. The first doped region is disposed in the substrate. The second doped region is disposed in the substrate. The well region and the first doped region form a first PN junction, the well region and the substrate form a second PN junction, and the substrate and the second doped region form a third junction. The first, second, and third PN junctions form the SCR, and the first doped region and the third PN junction form the diode.

Abstract: A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.

Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Abstract: Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.

Abstract: Provided is a metal oxide semiconductor device, including a substrate, a gate, a first-type first heavily doped region, a first-type drift region, a second-type first heavily doped region, a contact, a first electrode, and a second electrode. The gate is disposed on the substrate. The first-type first heavily doped region is disposed in the substrate at a side of the gate. The first-type drift region is disposed in the substrate at another side of the gate. The second-type first heavily doped region is disposed in the first-type drift region. The contact is electrically connected to the second-type first heavily doped region. The contact is the closest contact to the gate on the first-type drift region. The first electrode is electrically connected to the contact, and the second electrode is electrically connected to the first-type first heavily doped region and the gate.

Abstract: The present invention provides a device for electrostatic discharge and the method of manufacturing thereof. P-well is formed on the substrate, and a first N+ doped region, a second N+ doped region and a P+ doped region are formed in the P-well; both ends of each doped region adopt shallow trench isolation for isolation. A lightly doped source-drain region portion is formed between the first N+ doped region and the shallow trench isolation connected thereto. Under the source-drain region, a halo injection with an inverse type is formed. The reverse conduction voltage of the collector of the bipolar transistor is lowered through the introduction of special doped region and the adoption of lightly doped source-drain technology for manufacturing the source-drain region as well as the manufacturing of halo injection with inverse type under the source-drain region, thus reducing the trigger voltage of the device.

Abstract: Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.

Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit.

Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

Abstract: The present invention provides a programmable memory array including a plurality of memory cells. At least one and preferably each memory cell of the plurality of memory cells include an isolation layer formed of a dielectric material, a field effect transistor, and a programmable element. The programmable element includes a conductive gate, a gate insulator present beneath the conductive gate, and a semiconductor body present under the gate insulator. The semiconductor body of the programmable element is of a different doping type then the doping of the channel region of the field effect transistor. Apart from these components, the memory cell also includes a bit line connected to the source of the field effect transistor, a select word line connected to the gate of the field effect transistor and a program word line connected to the conductive gate of the programmable element.

Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.

Abstract: A protection circuit according to an embodiment of the present invention is provided between a first terminal and a second terminal and includes: a capacitor element having one end connected to the second terminal; and a multi-cathode thyristor formed on a semiconductor substrate, and including an anode connected to the first terminal, a first cathode connected to the second terminal, and a second cathode disposed between the anode and the first cathode and connected to another terminal of the capacitor element.

Abstract: A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technology. According to an example embodiment of the present invention, the semiconductor device includes a pass device having a channel in a fin portion over a semiconductor substrate, and a thyristor device coupled to the pass device. The fin has a top portion and a side portion and extends over the semiconductor substrate. The pass device includes source/drain regions separated by the channel and a gate facing and capacitively coupled to the side portion of the fin that includes the channel. The thyristor device includes anode and cathode end portions, each end portion having base and emitter regions, where one of the emitter regions is coupled to one of the source/drain regions of the pass device.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract: An integrated circuit is made of a semiconductor material and comprises an input and/or terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as to be biased at the same time as the parasitic element under the effect of an electrostatic discharge, and more than the parasitic element to evacuate a discharge current as a priority.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: An electrostatic discharge protection device for protecting a node includes a transistor, a silicon controlled rectifier, a second contact region laterally displaced from the first contact region, and a collection region adjacent the source region. The transistor includes a semiconductor substrate, a source region, a channel region adjacent the source region, a gate over the channel region, and a drain region laterally displaced from the channel. The silicon controlled rectifier includes the source region, a portion of the substrate, a doped well, and a first contact region in the well, laterally displaced from the drain region. The collection region, the source region and the gate, are metallically connected. The node, the first contact region, and the second contact region, are metallically connected, and the drain region is not metallically connected to the node.

Abstract: Integrating high-voltage devices with other circuitry, which may be fabricated on a semiconductor wafer using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, and the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The high-voltage devices may be used to create useful high-voltage circuits, such as level-shifting circuits, input protection circuits, charge pump circuits, switching circuits, latch circuits, latching switch circuits, interface circuits, any combination thereof, or the like. The high-voltage circuits may be controlled by the other circuitry.

Abstract: An ESD protection circuit includes a substrate, diode device, first snapback device, ring structure, second snapback device and a control circuit. The diode device is formed in the substrate. The first snapback device is formed in the substrate and includes a first heavy ion-doped region, a first gate and a second heavy ion-doped region. The first heavy ion-doped region is coupled to the diode device. The first gate is coupled to the second heavy ion-doped region. The ring structure is formed in the substrate and includes a third heavy ion-doped region located. The second gate is formed on the substrate between the second heavy ion-doped region and the third heavy ion-doped region to generate a second snapback device. The control circuit is connected to the third heavy ion-doped region for preventing the turn-on of a parasitic SCR formed in the substrate in a normal operation.

Abstract: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer.

Abstract: A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.

Abstract: An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.

Abstract: A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

Abstract: A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: A semiconductor device has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside of the gate forming areas in the active region. Recess gates are formed in the respective gate forming areas of the active region and depressed inward on the sidewalls of lower buried portions thereof formed in the substrate, which face the drain forming area, such that each of the lower buried portions has a decreased width, thereby creating an asymmetrical structure in which the distance between the lower buried portions of the recess gates is greater than the distance between upper buried portions of the recess gates. Source and drain areas formed on the surface of the substrate on both sides of the recess gates.

Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

Abstract: An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: A thyristor structure having a first terminal, formed as a first region with a first conductivity type, is provided. A second region of a second conductivity type adjoins the first region. A third region of the first conductivity type, which adjoins the second region, has a common surface with the latter. A second terminal, as fourth region of the second conductivity type, adjoins the third region. At the common surface of the second region and the third region, an auxiliary electrode is disposed in a manner adjoining at least one of the two regions.

Abstract: In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are formed.