With Delta-doped Channel (epo) Patents (Class 257/E29.254)
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Patent number: 9006828Abstract: A display device includes a first electrode, a second electrode, an organic light emitting layer, a first transistor, and a second transistor. The first transistor includes a first semiconductor layer, a first conductive unit, a second conductive unit, a first gate electrode, and a first gate insulating film. The second transistor includes a second semiconductor layer, a third conductive unit, a fourth conductive unit, a second gate electrode, and a second gate insulating film. An amount of hydrogen included in the first gate insulating film is larger than an amount of hydrogen included in the second gate insulating film.Type: GrantFiled: August 7, 2014Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Nobuyoshi Saito, Tomomasa Ueda, Yuya Maeda, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano, Hajime Yamaguchi
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Patent number: 8907378Abstract: A device includes a source and a drain for transmitting and receiving an electronic charge. The device also includes a first stack and a second stack for providing at least part of a conduction path between the source and the drain, wherein the first stack includes a first gallium nitride (GaN) layer of a first polarity, and the second stack includes a second gallium nitride (GaN) layer of the second polarity, and wherein the first polarity is different from the second polarity. At least one gate operatively connected to at least the first stack for controlling a conduction of the electronic charge, such that, during an operation of the device, the conduction path includes a first two-dimensional electron gas (2DEG) channel formed in the first GaN layer and a second 2DEG channel formed in the second GaN layer.Type: GrantFiled: March 15, 2013Date of Patent: December 9, 2014Assignee: Mitsubishi Electric Research Laboratories, Inc.Inventors: Koon Hoo Teo, Peijie Feng, Rui Ma
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Patent number: 8652959Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: GrantFiled: February 1, 2013Date of Patent: February 18, 2014Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A. Papanicolaou
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Patent number: 8633518Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: December 21, 2012Date of Patent: January 21, 2014Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Patent number: 8604549Abstract: A field-effect transistor has an extra gate above a shallow trench isolation (STI) to enhance and to adapt the low-frequency noise induced by an STI-silicon interface. By changing the voltage applied to the STI gate, the field-effect transistor is able to adapt its low-frequency noise over four decades. The field-effect transistor can be fabricated with a standard CMOS logic process without additional masks or process modification.Type: GrantFiled: November 18, 2011Date of Patent: December 10, 2013Assignee: National Tsing Hua UniversityInventors: Tang-Jung Chiu, Jeng Gong, Hsin Chen
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Patent number: 8482035Abstract: According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.Type: GrantFiled: January 31, 2011Date of Patent: July 9, 2013Assignee: International Rectifier CorporationInventor: Michael A. Briere
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Patent number: 8461664Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: GrantFiled: May 25, 2011Date of Patent: June 11, 2013Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A Papanicolaou
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Patent number: 8384130Abstract: Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode spaced apart from the drain electrode, in Schottky contact with the nitride semiconductor layer, and having an ohmic pattern in ohmic contact with the nitride semiconductor layer inside; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and a gate electrode disposed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.Type: GrantFiled: August 3, 2011Date of Patent: February 26, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Ki Yeol Park, Young Hwan Park
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Patent number: 8344424Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: February 28, 2012Date of Patent: January 1, 2013Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Patent number: 8264004Abstract: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.Type: GrantFiled: March 1, 2010Date of Patent: September 11, 2012Assignee: Intel CorporationInventors: Been-Yih Jin, Jack T. Kavalieros, Suman Datta, Amlan Majumdar, Robert S. Chau
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Patent number: 8193562Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: February 1, 2011Date of Patent: June 5, 2012Assignee: Tansphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Patent number: 8183595Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.Type: GrantFiled: July 28, 2006Date of Patent: May 22, 2012Assignee: International Rectifier CorporationInventor: Michael A. Briere
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Patent number: 7999314Abstract: A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.Type: GrantFiled: June 19, 2008Date of Patent: August 16, 2011Assignee: Denso CorporationInventors: Yukio Tsuzuki, Makoto Asai
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Patent number: 7915643Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: September 17, 2007Date of Patent: March 29, 2011Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Patent number: 7915642Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: December 30, 2008Date of Patent: March 29, 2011Assignee: Intel CorporationInventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Jack Kavalieros
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Patent number: 7859018Abstract: A semiconductor device having a GaN-based main semiconductor region formed on a silicon substrate via a buffer region. Source, drain and gate electrodes are formed on the main semiconductor region, and a back electrode on the back of the substrate. The substrate is constituted of two semiconductor regions of opposite conductivity types, with a pn junction therebetween which is conducive to a higher voltage-withstanding capability between the drain and back electrodes.Type: GrantFiled: July 20, 2006Date of Patent: December 28, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Shinichi Iwakami, Osamu Machida
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Patent number: 7777254Abstract: After creating an electron transit layer on a substrate, a baffle is formed on midpart of the surface of the electron transit layer, the surface having a pair of spaced-apart parts left on both sides of the baffle. A semiconducting material different from that of the electron transit layer is deposited on its surface thereby conjointly fabricating an electron supply layer grown continuously on the pair of spaced-apart parts of the electron transit layer surface, and a discontinuous growth layer on the baffle in the midpart of the electron transit layer surface. When no voltage is being impressed to the gate electrode on the discontinuous growth layer, this layer creates a hiatus in the two-dimensional electron gas layer generated along the heterojunction between the electron supply layer and electron transit layer. The hiatus is closed upon voltage application to the gate electrode.Type: GrantFiled: June 9, 2008Date of Patent: August 17, 2010Assignee: Sanken Electric Co., Ltd.Inventor: Ken Sato
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Patent number: 7700975Abstract: Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) layer deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. In one embodiment, the semiconductor layer is an intrinsic semiconductor layer. In one embodiment, the thickness of the delta doped layer is less than 100 nanometers. In one embodiment, the delta doped layer has a dopant concentration of at least 1×1018 cm?3. A delta doped layer is formed on portions of a semiconductor layer over a substrate. Metal contacts are formed on the delta doped layer. A buffer layer may be formed between the substrate and the semiconductor layer. In one embodiment, the substrate includes silicon, and the semiconductor layer includes germanium.Type: GrantFiled: March 31, 2006Date of Patent: April 20, 2010Assignee: Intel CorporationInventors: Titash Rakshit, Miriam Reshotko
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Patent number: 7663161Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.Type: GrantFiled: November 14, 2007Date of Patent: February 16, 2010Assignee: Panasonic CorporationInventors: Kazuhiro Kaibara, Masahiro Hikita, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Patent number: 7508014Abstract: A field effect transistor including an i-type first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer and having a band gap energy higher in magnitude than that of the first semiconductor layer. The first semiconductor layer and second semiconductor layer are each made of a gallium nitride-based compound semiconductor layer. A gate electrode is formed on the second semiconductor layer and a second electrode is formed on the first semiconductor layer. Thus, the field effect transistor is constructed in such a manner as the first semiconductor layer and second semiconductor layer are interposed between the gate electrode and the second electrode. Thus field effect transistor is able to discharge the holes that are accumulated in the channel from the elemental structure and to improve the withstand voltage of the field effect transistor.Type: GrantFiled: November 16, 2005Date of Patent: March 24, 2009Assignee: Nichia CorporationInventor: Masashi Tanimoto
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Patent number: 7473929Abstract: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.Type: GrantFiled: July 1, 2004Date of Patent: January 6, 2009Assignee: Panasonic CorporationInventors: Osamu Kusumoto, Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita, Masahiro Hagio, Kazuyuki Sawada
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Patent number: 7429747Abstract: A group III-V material CMOS device may have NMOS and PMOS portions that are substantially the same through several of their layers. This may make the CMOS device easy to make and prevent coefficient of thermal expansion mismatches between the NMOS and PMOS portions.Type: GrantFiled: November 16, 2006Date of Patent: September 30, 2008Assignee: Intel CorporationInventors: Mantu K. Hudait, Suman Datta, Jack T. Kavalieros, Mark L. Doczy, Robert S. Chau
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Publication number: 20080203441Abstract: A SiC semiconductor device having a MOS structure includes: a SiC substrate; a channel region providing a current path; first and second impurity regions on upstream and downstream sides of the current path, respectively; and a gate on the channel region through the gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 4.7×1020 cm?3. The interface provides a channel surface having a (000-1)-orientation surface.Type: ApplicationFiled: February 26, 2008Publication date: August 28, 2008Applicant: DENSO CORPORATIONInventor: Takeshi Endo