Abstract: A flat panel display device including a substrate including first and second regions; an active layer on the first region of the substrate including a semiconductor material; a lower electrode on the second region of the substrate including the semiconductor material; a first insulating layer on the substrate including the active layer and the lower electrode thereon; a gate electrode on the first insulating layer overlying the active layer and including a first conductive layer pattern and a second conductive layer pattern; an upper electrode on the first insulating layer overlying the lower electrode and including the first conductive layer pattern and the second conductive layer pattern; a second insulating layer on the gate electrode and the upper electrode exposing portions of the active layer and portions of the upper electrode; and a source electrode and a drain electrode connected to the exposed portions of the active layer.

Abstract: A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.

Abstract: A non-linear element (e.g., a diode) with small reverse saturation current is provided. A non-linear element includes a first electrode provided over a substrate, an oxide semiconductor film provided on and in contact with the first electrode, a second electrode provided on and in contact with the oxide semiconductor film, a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode, and a third electrode provided in contact with the gate insulating film and adjacent to a side surface of the oxide semiconductor film with the gate insulating film interposed therebetween or a third electrode provided in contact with the gate insulating film and surrounding the second electrode. The third electrode is connected to the first electrode or the second electrode.

Abstract: A semiconductor device includes: a first vertical type transistor having a first lower diffusion layer, a first upper diffusion layer, and a gate electrode; a second vertical type transistor having a second lower diffusion layer, a second upper diffusion layer, and a second gate electrode; a gate wiring connected to the first and second gate electrodes; a first wiring connected to the first lower diffusion layer and second upper diffusion layer; and a second wiring connected to the first upper diffusion layer and second lower diffusion layer.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin. A gate spacer is formed around the gate stack. A raised source region and a raised drain region are epitaxially formed on the source/drain extension regions. The source/drain extension regions are self-aligned to sidewalls of the gate stack, and thus ensure a sufficient overlap with the gate electrode. Further, the combination of the source/drain extension regions and the raised source/drain regions provides a low-resistance path to the channel of the field effect transistor.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: An electrical circuit includes first and second transistors. Each transistor includes a substrate and, positioned thereon, a first electrically conductive material layer including a reentrant profile functioning as a gate. First and second discrete portions of a second electrically conductive material layer are in contact with first and second portions, respectively, of a semiconductor material layer in contact with an electrically insulating material layer, both of which conform to the reentrant profile. The first and second discrete portions are source/drain and drain/source electrodes of the first and second transistors, respectively. A third electrically conductive material layer, in contact with a third portion of the semiconductor material layer, is positioned over the gate, but is not in electrical contact with it.

Abstract: An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.

Abstract: A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Abstract: Embodiments of the invention relate to field effect transistors. The field effect transistor includes a gate electrode for providing a gate field, a first electrode including a conductive material having a low carrier density and a low density of electronic states, a second electrode, and a semiconductor. Contact barrier modulation includes barrier height lowering of a Schottky contact between the first electrode and the semiconductor. In some embodiments of the invention, a vertical field effect transistor employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.

Abstract: An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.

Abstract: A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.

Abstract: A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type.

Abstract: To provide a miniaturized semiconductor device with stable electric characteristics in which a short-channel effect is suppressed. Further, to provide a manufacturing method of the semiconductor device. The semiconductor device (transistor) including a trench formed in an oxide insulating layer, an oxide semiconductor film formed along the trench, a source electrode and a drain electrode which are in contact with the oxide semiconductor film, a gate insulating layer over the oxide semiconductor film, a gate electrode over the gate insulating layer is provided. The lower corner portions of the trench are curved, and the side portions of the trench have side surfaces substantially perpendicular to the top surface of the oxide insulating layer. Further, the width between the upper ends of the trench is greater than or equal to 1 time and less than or equal to 1.5 times the width between the side surfaces of the trench.

Abstract: A method of forming a semiconductor device includes the following processes. A first pillar and a second pillar are formed on a semiconductor substrate. A semiconductor film is formed which includes first and second portions. The first portion is disposed over a side surface of the first pillar. The second portion is disposed over a side surface of the second pillar. The first and second portions are different from each other in at least one of impurity conductivity type and impurity concentration. A part of the semiconductor film is removed by etching back. The first and second portions are etched at first and second etching rates that are different from each other.

Abstract: A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.

Abstract: It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.

Abstract: A vertical thin film transistor and a method for manufacturing the same and a display device including the vertical thin film transistor and a method for manufacturing the same are disclosed. The vertical thin film transistor is applied to a substrate. In the present invention, a gate layer of the vertical thin film transistor is formed to have a plurality of concentric annular structures and the adjacent concentric annular structures are linked. By the concentric annular structures of the gate electrode layer, resistance to stress and an on-state current of the vertical thin film transistor can be increased.

Abstract: A display apparatus includes a first substrate including a plurality of pixels, a second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. Each pixel includes a gate electrode, a gate insulating layer, a semiconductor pattern, a source electrode, a drain electrode, a first electrode, and a second electrode. The first electrode includes a first portion overlapping the drain electrode and a second portion outside the first portion, and the second electrode does not overlap the first portion of the first electrode. The first electrode or the second electrode is formed as a single unitary structure.

Abstract: A semiconductor device in which improvement of a property of holding stored data can be achieved. Further, power consumption of a semiconductor device is reduced. A transistor in which a wide-gap semiconductor material capable of sufficiently reducing the off-state current of a transistor (e.g., an oxide semiconductor material) in a channel formation region is used and which has a trench structure, i.e., a trench for a gate electrode and a trench for element isolation, is provided. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor enables data to be held for a long time. Further, since the transistor has the trench for a gate electrode, the occurrence of a short-channel effect can be suppressed by appropriately setting the depth of the trench even when the distance between the source electrode and the drain electrode is decreased.

Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Abstract: Provided is a polysilicon thin film transistor having a trench type bottom gate structure using copper and a method of making the same. The polysilicon thin film transistor includes: a transparent insulation substrate; a seed pattern that is formed in a pattern corresponding to that of a gate electrode on the transparent insulation substrate, and that is used to form the gate electrode; a trench type guide portion having a trench type contact window in which an upper portion of the seed pattern is exposed; the gate electrode that is formed by electrodepositing copper on a trench of the exposed seed pattern; a gate insulation film formed on the upper portions of the gate electrode and the trench type guide portion, respectively; and a polysilicon layer in which a channel region, a source region and a drain region are formed on the upper portion of the gate insulation film.

Abstract: Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound

Abstract: A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.

Abstract: A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.

Abstract: To provide a semiconductor device in which a channel formation region can be thinned without adversely affecting a source region and a drain region through a simple process and a method for manufacturing the semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film, having a thickness smaller than a height of a projection of a substrate, is formed over a surface of the substrate having the projections; the semiconductor film is etched to have an island shape with a resist used as a mask; the resist is etched to expose a portion of the semiconductor film which covers a top surface of the projection; and the exposed portion of the semiconductor film is etched to be thin, while the adjacent portions of the semiconductor film on both sides of the projection remain covered with the resist.

Abstract: A display substrate according to the present invention comprises a gate line formed on a substrate, a data line, a thin film transistor connected to the gate line and the data line respectively and pixel electrode connected to the thin film transistor, wherein a channel of the thin film transistor is formed in a direction perpendicular to the substrate and, a layer where the channel is formed includes an oxide semiconductor pattern. ON current of thin film transistor of the display substrate can be increased without loss of aperture ratio.

Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions.

Abstract: A first transistor in which an image signal is input to one of a first source and a first drain through an image signal line and a first scan signal is input to the first gate through a first scan signal line; a capacitor whose one of two electrodes is electrically connected to the other of the first source and the first drain of the first transistor; a second transistor in which one of a second source and a second drain is electrically connected to the other of the first source and the first drain of the first transistor and a second scan signal is input to a second gate through a second scan signal line; and a liquid crystal element whose first electrode is electrically connected to the other of the second source and the second drain of the second transistor.

Abstract: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.

Abstract: A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.

Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.

Abstract: A capacitorless DRAM and methods of manufacturing and operating the same are provided. The capacitorless DRAM includes a source, a drain and a channel layer, formed on a substrate. A charge reserving layer is formed on the channel layer. The capacitorless DRAM includes a gate that contacts the channel layer and the charge reserving layer.

Abstract: A thin film transistor for an organic light emitting display device is disclosed. In one embodiment, the thin film transistor includes: a substrate, an active layer formed over the substrate, wherein the active layer is formed of an oxide semiconductor, a gate insulating layer formed over the substrate and the active layer, and source and drain electrodes formed on the gate insulating layer and electrically connected to the active layer. The transistor may further include a gate electrode formed on the gate insulating layer and formed between the source and drain electrodes, wherein the gate electrode is spaced apart from the source electrode so as to define a first offset region therebetween, and wherein the gate electrode is spaced apart from the drain electrode so as to define a second offset region therebetween.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; a fin formed on the semiconductor substrate; a gate electrode formed so as to sandwich both side faces of the fin between its opposite portions via a gate insulating film; an extension layer formed on a region of a side face of the fin, the region being on the both sides of the gate electrode, the extension layer having a plane faced to a surface of the semiconductor substrate at an acute angle; and a silicide layer formed on a surface of the plane faced to the surface of the semiconductor substrate at an acute angle.

Abstract: The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the recess channel region. The gate structure is disposed over the recess channel region of the gate region.

Abstract: A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.

Abstract: A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.

Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.

Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode comprising an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion comprises an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.

Abstract: Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.

Abstract: A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer.

Abstract: The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).

Abstract: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.

Abstract: The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the recess channel region. The gate structure is disposed over the recess channel region of the gate region.

Abstract: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a view to forming double layered silicon-metal nanocrystals by self-alignment.

Abstract: In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.