With Light Shield (epo) Patents (Class 257/E29.282)
  • Patent number: 9041147
    Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Patent number: 8853758
    Abstract: There is provided a solid-state imaging device including plural pixel regions, each including a pixel having a photoelectric conversion unit, a color filter, and a microlens that condenses the incident light to the photoelectric conversion unit; a first light shielding portion that has a first end face at the side of the microlens, and a second end face opposite to the first end face, and that is formed at each side portion of each pixel region of the plurality of the pixel regions; and a second light shielding portion that has a first end face at the side of the microlens, and a second end face opposite to the first end face, and that is formed at each corner portion of the pixel region, in which a distance from a surface of the pixel to the first end face is short compared to the first light shielding portion.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: October 7, 2014
    Assignee: Sony Corporation
    Inventor: Yoichi Ootsuka
  • Patent number: 8729678
    Abstract: An image sensor includes first pixels, second pixels and a deep trench. The first pixels are formed in an active region of a semiconductor substrate, and configured to measure photo-charges corresponding to incident light. The second pixels are formed in an optical-black region of the semiconductor substrate, and are configured to measure black levels. The deep trench is formed vertically in a boundary region of the optical-black region, where the boundary region is adjacent to the active region, and configured to block leakage light and diffusion carriers from the active region.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Sub Shim, Jung-Chak Ahn, Moo-Sup Lim, Hyung-Jin Bae, Min-Seok Oh
  • Patent number: 8026506
    Abstract: In a thin-film transistor comprising respective elements of: three electrodes of a source electrode, a drain electrode and a gate electrode; a channel layer; and a gate insulating film, at least the channel layer is formed by a metal oxide film including indium. Therefore, it is possible to obtain the thin-film transistor, which can manufacture an element to a polymer substrate without using a high temperature process and which can achieve a high performance and a high reliability at low cost.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: September 27, 2011
    Assignee: Bridgestone Corporation
    Inventors: Osamu Shiino, Yoshinori Iwabuchi, Ryo Sakurai, Tatsuya Funaki
  • Patent number: 7829393
    Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: November 9, 2010
    Assignee: Au Optronics Corp.
    Inventors: Yu-Wei Liu, Wen-Ching Tsai, Kuo-Yu Huang, Hui-Fen Lin
  • Patent number: 7808004
    Abstract: A light emitting diode package structure having a heat-resistant cover and a method of manufacturing the same include a base, a light emitting diode chip, a plastic shell, and a packaging material. The plastic shell is in the shape of a bowl and has an injection hole thereon. After the light emitting diode chip is installed onto the base, the plastic shell is covered onto the base to fully and air-tightly seal the light emitting diode chip, and the packaging material is injected into the plastic shell through the injection hole until the plastic shell is filled up with the packaging material to form a packaging cover, and finally the plastic shell is removed to complete the LED package structure.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: October 5, 2010
    Assignee: Edison Opto Corporation
    Inventors: Tsung-Ting Sun, Hung-Ta Laio, Hung-Hsun Chou, Tz-Shiuan Yan, Kuo-Shih Hsu
  • Patent number: 7804096
    Abstract: A semiconductor device includes: a substrate; a plurality of island-shaped light shielding films formed on the substrate; a first insulating film formed between the plurality of light shielding films; a second insulating film formed on the first insulating film and the plurality of light shielding films; and semiconductor elements each having a semiconductor film. The step difference is not generated between an interface between the first insulating film and the second insulating film and an interface between each of the plurality of light shielding films and the second insulating film. Each of the plurality of light shielding films is disposed between each of the semiconductor films and the substrate.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: September 28, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Hiroaki Jiroku
  • Patent number: 7795621
    Abstract: A thin film transistor panel including: a transparent substrate; scanning lines made of a light blocking electroconductive material to be formed on the transparent substrate; data lines formed on the transparent substrate to be perpendicular to the scanning lines and made of a light blocking electroconductive material; thin film transistors, each provided with a transparent gate electrode connected to one of the scanning lines, a transparent drain electrode connected to one of the data lines, a transparent source electrode and a transparent semiconductor thin film; and transparent pixel electrodes connected to the thin film transistors, wherein each of the pixel electrodes is formed to cover at least a part of the gate electrode of each of the thin film transistors.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: September 14, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ikuhiro Yamaguchi, Manabu Takei, Motohiko Yoshida
  • Patent number: 7777228
    Abstract: An array substrate for a liquid crystal display device comprises a gate line on a substrate having a pixel region; a gate insulating layer on the gate line; a data line crossing the gate line to define the pixel region and formed on the gate insulating layer; a thin film transistor in the pixel region and connected to the gate line and the data line; a passivation layer on the thin film transistor and the data line and having a groove extending along boundary portion of the pixel region and exposing the gate insulating layer; and a pixel electrode in the pixel region and connected to the thin film transistor.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: August 17, 2010
    Assignee: LG Display Co., Ltd.
    Inventor: Ji-Hyun Jung
  • Patent number: 7679157
    Abstract: An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel electrodes, and a transparent conductive layer covering the photo conductive layer.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: March 16, 2010
    Assignee: Powerchip Semiconductor Corp.
    Inventor: Takashi Miida
  • Patent number: 7671363
    Abstract: In at least one embodiment of the disclosure, an electro-optical device includes a peripheral circuit wiring arranged in a peripheral area located peripheral to a pixel area. The peripheral circuit wiring has overlapping portions that overlap vertical conduction terminals in plan view. The overlapping portions are arranged on a lower layer side relative to the vertical conduction terminals. An insulating film electrically insulates the overlapping portions of the peripheral circuit wiring from the vertical conduction terminals.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: March 2, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Masao Murade
  • Patent number: 7646023
    Abstract: A thin film transistor (TFT) array panel effectively minimizing light leakage current and a liquid crystal display including the same. The panel includes a transistor structure having a gate electrode formed on an insulating substrate; a semiconductor layer formed on and insulated from the gate electrode; a light blocking layer formed around and overlapping a portion of the gate electrode; a data line intersecting the gate line to form a source electrode, which overlaps a portion of the semiconductor layer; a drain electrode opposing to the source electrode and overlapping a portion of the semiconductor layer, and a pixel electrode formed on and insulated from the transistor structure and electrically connected to the drain electrode.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: January 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-han Park, Jin Jeon
  • Patent number: 7633090
    Abstract: A thin film transistor panel, including: a transparent substrate; scanning lines made of a transparent electroconductive material, formed on the transparent substrate; data lines formed on the transparent substrate to be perpendicular to the scanning lines; thin film transistors, each provided with a transparent gate electrode connected to one of the scanning lines, a transparent drain electrode connected to one of the data line, a transparent source electrode and a transparent semiconductor thin film; and transparent pixel electrodes connected to the thin film transistors, wherein each of the pixel electrodes is formed to cover each of the thin film transistors.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: December 15, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiromitsu Ishii
  • Publication number: 20090278129
    Abstract: A liquid crystal display device includes a gate line and a data line crossing each other to define a pixel region on a substrate, a gate electrode connected to the gate line, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, source and drain electrodes on the active layer, spaced apart from each other and each having inner sides that face each other, wherein the source electrode is connected to the data line, ohmic contact layers between the active layer and each of the source and drain electrodes, a shielding pattern over the active layer and having outer sides, wherein at least one of the outer sides faces at least one of the inner sides of the source and drain electrodes, and a pixel electrode in the pixel region and connected to the drain electrode.
    Type: Application
    Filed: July 21, 2009
    Publication date: November 12, 2009
    Applicant: LG DISPLAY CO., LTD.
    Inventors: Hyo-Uk KIM, Byoung-Ho LIM
  • Publication number: 20090261335
    Abstract: A self-illumination display is provided, including a first substrate, a light-absorbing structure, a filter layer, a driving circuit unit, and a self-illumination unit. The light-absorbing structure and the filter layer are juxtaposedly disposed over the first substrate. The driving circuit unit is disposed over and shielded by the light-absorbing structure. The self-illumination unit is disposed over the filter layer, including a light-transmissible electrode, a light emitting layer, and a black electrode. The self-illumination unit is disposed over the filter layer, including a light-transmissible electrode, a light emitting layer, and a black electrode. The light-transmissible electrode is disposed over the filter layer while the light emitting layer and the black electrode are sequentially tiered on the light-transmissible electrode. The light-absorbing structure, the filter layer and the black electrode together reduce the reflection of the ambient light and enhance the image contrast.
    Type: Application
    Filed: July 1, 2009
    Publication date: October 22, 2009
    Inventor: Chung-Chun Lee
  • Patent number: 7601566
    Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: October 13, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hideto Ohnuma, Hideaki Kuwabara
  • Patent number: 7563658
    Abstract: The present invention relates to a method for manufacturing a semiconductor film, including the steps of forming a transparent conductive film, forming a first conductive film over the transparent conductive film, forming a second conductive film over the first conductive film, etching the second conductive film with a gas including chlorine, and etching the first conductive film with a gas including fluorine. During etching of the second conductive film with a gas including chlorine, the transparent conductive film is protected by the first conductive film. During etching of the first conductive film with the gas including fluorine, the transparent conductive film does not react with the gas including fluorine. Therefore, no particle is formed.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: July 21, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Satoru Okamoto, Shigeharu Monoe, Shunpei Yamazaki
  • Patent number: 7528466
    Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: May 5, 2009
    Assignee: AU Optronics Corp.
    Inventors: Yu-Wei Liu, Wen-Ching Tsai, Kuo-Yu Huang, Hui-Fen Lin
  • Patent number: 7507598
    Abstract: A method is provided for processing a substrate. The substrate has at least one filter region, a plurality of bond pads, and a plurality of scribe lines arranged around the filter region and bond pads. A first planarization layer is formed above the substrate. The planarization layer has a substantially flat top surface overlying the filter region, the bond pads and the scribe lines. At least one color resist layer is formed over the first planarization layer and within the filter region while the first planarization layer covers the bond pads and the scribe lines.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: March 24, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Tien Weng, Yu-Kung Hsiao, Hung-Jen Hsu, Yi-Ming Dai, Chin Chen Kuo, Te-Fu Tseng, Chih-Kung Chang, Jack Deng, Chung-Sheng Hsiung, Bii-Junq Chang
  • Patent number: 7474002
    Abstract: In the semiconductor device having a structure in which a plurality of layers are built-up by layers made of different materials or layers including various formed patterns, it is an object to provide a method which smoothing surface can be achieved without a polishing treatment by CMP method or a smoothing process by depositing a SOG film, a substrate material is not chosen, and the smoothing is simple and easy. In the semiconductor device in which a plurality of different layers are formed, smoothing surface can be achieved without the polishing treatment by the CMP method or the smoothing process by depositing the SOG film to a dielectric film formed on a dielectric film and a wring (electrode) or a semiconductor layer in a manner that an aperture portion is formed in the dielectric film, the wring (electrode) or the semiconductor layer is formed in the aperture portion.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: January 6, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akira Ishikawa
  • Patent number: 7271048
    Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: September 18, 2007
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chien-Ping Chang, Mao Song Tseng, Hsin Huang Hsieh, Tien-Min Yuan
  • Publication number: 20070200139
    Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.
    Type: Application
    Filed: April 27, 2007
    Publication date: August 30, 2007
    Inventors: Hiroshi Shibata, Shinji Maekawa
  • Patent number: 6964916
    Abstract: A method for processing a semiconductor substrate includes providing a substrate having at least one filter region with a plurality of bond pads in it. Metal is deposited above the bond pads, to reduce the bond pad step height. A planarization layer is formed such that the deposited metal has a height near to a height of the planarization layer. At least one color resist layer is formed above the planarization layer.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 15, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin Chen Kuo, Chih-Kung Chang, Hung-Jen Hsu, Fu-Tien Weng, Te-Fu Tseng
  • Patent number: RE41927
    Abstract: In a TFT LCD device comprising a substrate, at least one thin film transistor formed on the substrate, having a source electrode and a drain electrode, an insulating layer formed over the whole surface of the substrate on which the thin film transistor is formed, having at least one contact hole exposing a portion of the drain electrode, and reflective layer pixel electrode corresponding to the thin film transistor, formed on the insulating layer to be connected with the drain electrode through the contact hole, the pixel electrode is formed of a multi-layered conductive layer. The drain electrode is composed of multiple layers, and the most upper layer of the multiple layers is one selected from a Cr layer and a MoW layer. Preferably, the multi-layered conductive layer is composed of two-layered conductive layer having a lower layer of the same material as that of the most upper layer and an upper layer of Al-containing metal.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Suk Chung, Chang-Won Hwang