Characterized By Insulating Substrate Or Support (epo) Patents (Class 257/E29.295)
  • Publication number: 20080121889
    Abstract: A semiconductor device includes a thin-film transistor including a polycrystalline silicon layer, disposed above a substrates serving as an active layer. The thin-film transistor includes a first thin-film transistor section including a first channel region disposed in a drain-side portion of the polycrystalline silicon layer and also includes a second thin-film transistor section including a second channel region that is adjacent to the first channel region with an impurity-implanted region disposed therebetween. The first and second thin-film transistor sections are of the same conductivity type. The gate electrode of the first thin-film transistor section is electrically connected to the gate electrode of the second thin-film transistor section. The first thin-film transistor section has a channel length of less than 2 ?m.
    Type: Application
    Filed: October 23, 2007
    Publication date: May 29, 2008
    Applicant: Seiko Epson Corporation
    Inventor: Hideto ISHIGURO
  • Publication number: 20070252206
    Abstract: A thin film semiconductor transistor structure has a substrate with a dielectric surface, and an active layer made of a semiconductor thin film exhibiting a crystallinity as equivalent to the single-crystalline. To fabricate the transistor, the semiconductor thin film is formed on the substrate, which film includes a mixture of a plurality of crystals which may be columnar crystals and/or capillary crystal substantially parallel to the substrate. The resultant structure is then subject to thermal oxidation in a chosen atmosphere containing halogen, thereby removing away any metallic element as contained in the film. This may enable formation of a mono-domain region in which the individual columnar or capillary crystal is in contact with any adjacent crystals and which is capable of being substantially deemed to be a single-crystalline region without presence or inclusion of any crystal grain boundaries therein. This region is for use in forming the active layer of the transistor.
    Type: Application
    Filed: February 2, 2007
    Publication date: November 1, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Jun Koyama, Akiharu Miyanaga, Takeshi Fukunaga
  • Publication number: 20070228473
    Abstract: The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.
    Type: Application
    Filed: June 5, 2007
    Publication date: October 4, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diane Boyd, Bruce Doris, Meikei Ieong, Devendra Sadana
  • Patent number: 7259388
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: August 21, 2007
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 7193280
    Abstract: One-transistor ferroelectric memory devices using an indium oxide film (In2O3), an In2O3 film structure, and corresponding fabrication methods have been provided. The method for controlling resistivity in an In2O3 film comprises: depositing an In film using a PVD process, typically with a power in the range of 200 to 300 watts; forming a film including In overlying a substrate material; simultaneously (with the formation of the In-including film) heating the substrate material, typically the substrate is heated to a temperature in the range of 20 to 200 degrees C.; following the formation of the In-including film, post-annealing, typically in an O2 atmosphere; and, in response to the post-annealing: forming an In2O3 film; and, controlling the resistivity in the In2O3 film. For example, the resistivity can be controlled in the range of 260 to 800 ohm-cm.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 20, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Sheng Teng Hsu
  • Patent number: 7176490
    Abstract: It is a problem to provide a semiconductor device production system using a laser crystallization method capable of preventing grain boundaries from forming in a TFT channel region and further preventing conspicuous lowering in TFT mobility due to grain boundaries, on-current decrease or off-current increase. An insulation film is formed on a substrate, and a semiconductor film is formed on the insulation film. Due to this, preferentially formed is a region in the semiconductor film to be concentratedly applied by stress during crystallization with laser light. Specifically, a stripe-formed or rectangular concavo-convex is formed on the semiconductor film. Continuous-oscillation laser light is irradiated along the striped concavo-convex or along a direction of a longer or shorter axis of rectangle.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: February 13, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Shunpei Yamazaki, Mai Akiba
  • Patent number: 6710411
    Abstract: A method for crystallizing an amorphous silicon film which includes the steps of: preparing a substrate having the amorphous silicon film, the amorphous silicon film being formed on an intermediate layer in which an inner space exists; applying an energy to the amorphous silicon film in order to crystallize the amorphous silicon film, wherein the step of preparing the substrate includes the steps of: forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, forming the amorphous silicon film on the intermediate layer, selectively removing the amorphous silicon film and the intermediate layer to expose a part of the material layer for forming space, and removing the material layer for forming space; or forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, selectively removing the intermediate layer to expose a part of the material layer, removing the mate
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: March 23, 2004
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Dae-Gyu Moon