Abstract: A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer. Diffusion layers reside in upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer to form. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A contact resides on the metal gate line and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of the contact.

Abstract: This semiconductor device includes a silicon carbide layer of a first conductivity type having first and second principal surfaces and including an element region and a terminal region surrounding the element region on the first principal surface. The silicon carbide layer includes a first dopant layer of the first conductivity type contacting with the first principal surface and a second dopant layer of the first conductivity type located closer to the second principal surface than the first dopant layer is. The terminal region has, in its surface portion with a predetermined depth under the first principal surface, a terminal structure including respective portions of the first and second dopant layers and a ring region of a second conductivity type running through the first dopant layer to reach the second dopant layer. The dopant concentration of the first dopant layer is twice to five times as high as that of the second dopant layer 22.

Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

Abstract: Disclosed herein is a graphene device having a structure in which a physical gap is provided so that the off-state current of the graphene device can be significantly reduced without having to form a band gap in graphene, and thus the on/off current ratio of the graphene device can be significantly increased while the high electron mobility of graphene is maintained.

Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.

Abstract: Provided is a connecting part for a semiconductor device including a semiconductor element, a frame, and a connecting part which connects the semiconductor element and the frame to each other, in which an interface between the connecting part and the semiconductor element and an interface between the connecting part and the frame respectively have the area of Al oxide film which is more than 0% and less than 5% of entire area of the respective interfaces. The connecting part has an Al-based layer and first and second Zn-based layers on main surfaces of the Al-based layer, a thickness ratio of the Al-based layer relative to the Zn-based layers being less than 0.59.

Abstract: The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.

Abstract: A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer.

Abstract: Manufacturing a semiconductor structure including: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material.

Abstract: An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

Abstract: There is provided an amorphous oxide semiconductor including hydrogen and at least one element of indium (In) and zinc (Zn), the amorphous oxide semiconductor containing one of hydrogen atoms and deuterium atoms of 1×1020 cm?3 or more to 1×1022 cm?3 or less, and a density of bonds between oxygen and hydrogen except bonds between excess oxygen (OEX) and hydrogen in the amorphous oxide semiconductor being 1×1018 cm?3 or less.

Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.

Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silica particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.

Abstract: A MOSFET capable of achieving decrease in the number of steps in a manufacturing process and improvement in integration includes an SiC wafer composed of silicon carbide and a source contact electrode arranged in contact with the SiC wafer and containing titanium, aluminum, silicon, and carbon as well as a remaining inevitable impurity. The SiC wafer includes an n+ source region having an n conductivity type and a p+ region having a p conductivity type. Both of the n+ source region and the p+ region are in contact with the source contact electrode. The source contact electrode contains aluminum and titanium in a region including an interface with the SiC wafer.

Abstract: A semiconductor element including a substrate and at least one shallow junction formed in the substrate wherein doping atoms are disposed in the shallow junction. A plurality of carbide precipitates and micro-cavities is disposed in the substrate below the at least one shallow junction.

Abstract: A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process.

Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

Abstract: Disclosed herein is a graphene device having a structure in which a physical gap is provided so that the off-state current of the graphene device can be significantly reduced without having to form a band gap in graphene, and thus the on/off current ratio of the graphene device can be significantly increased while the high electron mobility of graphene is maintained.

Abstract: An object is to reduce the adverse influence which a portion of a gate insulating layer where the thickness has decreased, that is, a step portion, has on semiconductor element characteristics so that the reliability of the semiconductor element is improved. A semiconductor layer is formed over an insulating surface; a side surface of the semiconductor layer is oxidized using wet oxidation to form a first insulating layer; a second insulating layer is formed over the semiconductor layer and the first insulating layer; and a gate electrode is formed over the semiconductor layer and the first insulating layer with the second insulating layer interposed therebetween.

Abstract: A high performance field-effect transistor includes a substrate, a nanomaterial thin film disposed on the substrate, a source electrode and a drain electrode formed on the nanomaterial thin film, and a channel area defined between the source electrode and the drain electrode. A unitary self-aligned gate electrode extends from the nanomaterial thin film in the channel area between the source electrode and the drain electrode, the gate electrode having an outer dielectric layer and including a foot region and a head region, the foot region in contact with a portion of the nanomaterial thin film in the channel area. A metal layer is disposed over the source electrode, the drain electrode, the head region of the gate electrode, and portions of the nanomaterial thin film proximate the source electrode and the drain electrode in the channel area.

Abstract: A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.

Abstract: The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.

Abstract: Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Abstract: Provided is a graphene device and a method of manufacturing the same. The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.

Abstract: According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region is formed in the germanium layer adjacent to a channel region underlying the gate and overlaying the BOX layer, and a drain region is formed in the germanium layer adjacent to the channel region. The source region and the drain region are implanted with a p-type dopant. In one embodiment, a p-channel GOI one transistor memory cell is implemented as a capacitorless dynamic random access memory (DRAM) cell. In one embodiment, a plurality of p-channel GOI one transistor memory cells are included in a memory array.

Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed a carbon layer; annealing the SiC layer to activate the impurity; and removing the carbon layer. The annealing the SiC layer includes: increasing a temperature of the SiC layer from a second temperature to a first temperature within a first time duration; and decreasing the temperature of the SiC layer from the first temperature to the second temperature within a second time duration. The first temperature is equal to or higher than 1800° C., and the second temperature is lower than 1800° C. The first and second time durations are small.

Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.

Abstract: Provided are a thin film transistor in which an oxide semiconductor combined with a nitride containing boron or aluminum is applied to a channel layer and a method of fabricating the same. The thin film transistor in which an oxide semiconductor combined with a nitride containing boron or aluminum is applied to a channel layer exhibits significantly improved mobility and increased stability at a high temperature.

Abstract: A semiconductor device is provided which is capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the strained silicon layer and silicon-germanium layer.

Abstract: Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration of 3.0×1013 cm?2 or more in areal density, wherein a depth from the junction position formed between the diffusion region and the semiconductor substrate to the bottom of the F-containing NiSi layer is confined within the range of 20 to 100 nm, and the concentration of F atoms at an interface between the F-containing NiSi layer and the semiconductor substrate is 8.0×1018 cm?3 or more.

Abstract: Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1019 cm?3 or less.

Abstract: A method for manufacturing a semiconductor substrate including: epitaxially growing a silicon germanium (SiGe) film on a silicon (Si) substrate by a chemical vapor deposition method; subjecting a heat treatment to the SiGe film at a temperature of not less than 700° C. and not more than 1200° C.; implanting hydrogen ions into a surface of the SiGe film; subjecting a surface activation treatment to a main surface of at least one of the SiGe film and a support substrate; bonding main surfaces of the SiGe film and the support substrate at a temperature of not less than 100° C. and not more than 400° C.; and applying an external impact to a bonding interface between the SiGe film and the support substrate to delaminate the SiGe crystal along a hydrogen ion implanted interface of the SiGe film, thereby forming a SiGe thin film on the main surface of the support substrate.

Abstract: A silicon carbide semiconductor device is disclosed. The silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type and located on a first surface of the substrate; and a vertical type semiconductor element. The vertical type semiconductor element includes: an impurity layer having a second conductivity type, and located in a surface portion of the drift layer; and a first conductivity type region located in the drift layer, spaced away from the impurity layer, located closer to the substrate than the impurity layer, and having an impurity concentration higher than the drift layer.

Abstract: A semiconductor power device includes a plurality of closed N-channel MOSFET cells surrounded by trenched gates constituting substantially a square or rectangular cell. The trenched gates are further extended to a gate contact area and having greater width as wider trenched gates for electrically contacting a gate pad wherein the semiconductor power device further includes a source region disposed only in regions near the trenched gates in the closed N-channel MOSFET cells and away from regions near the wider trenched gate whereby a device ruggedness is improved. The source region is further disposed at a distance away from a corner or an edge of the semiconductor power device and away from a termination area. The semiconductor device further includes multiple trenched rings disposed in a termination area opposite the active area and the trenched rings having a floating voltage. The closed N-channel MOSFET cells are further supported on a red phosphorous substrate.

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Abstract: A high performance thin film transistor includes a flexible substrate, a layer of metal oxide semiconductor material deposited on the flexible substrate, and a layer of self-assembled organic gate dielectric material deposited on the metal oxide semiconductor material. The metal oxide semiconductor material has high carrier mobility and is transparent. An interface is formed between the layer of metal oxide semiconductor material and the layer of organic gate dielectric material that is substantially free of reactions and Fermi level pinning. The polymer materials are not polar and do not give rise to gap state formation and interface scattering.

Abstract: A method for making a thin film transistor, the method comprising the steps of: providing a growing substrate; applying a catalyst layer on the growing substrate; heating the growing substrate with the catalyst layer in a furnace with a protective gas therein, supplying a carbon source gas and a carrier gas at a ratio ranging from 100:1 to 100:10, and growing a carbon nanotube layer on the growing substrate; forming a source electrode, a drain electrode, and a gate electrode; and covering the carbon nanotube layer with an insulating layer, wherein the source electrode and the drain electrode are electrically connected to the single-walled carbon nanotube layer, the gate electrode is opposite to and electrically insulated from the single-walled carbon nanotube layer.

Abstract: Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration of 3.0×1013 cm?2 or more in areal density, wherein a depth from the junction position formed between the diffusion region and the semiconductor substrate to the bottom of the F-containing NiSi layer is confined within the range of 20 to 100 nm, and the concentration of F atoms at an interface between the F-containing NiSi layer and the semiconductor substrate is 8.0×1018 cm?3 or more.

Abstract: According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region is formed in the germanium layer adjacent to a channel region underlying the gate and overlaying the BOX layer, and a drain region is formed in the germanium layer adjacent to the channel region. The source region and the drain region are implanted with a p-type dopant. In one embodiment, a p-channel GOI one transistor memory cell is implemented as a capacitorless dynamic random access memory (DRAM) cell. In one embodiment, a plurality of p-channel GOI one transistor memory cells are included in a memory array.

Abstract: A resonant transistor includes a substrate, a source and a drain formed on the substrate, an input electrode and a carbon nanotube gate. A gap is formed between the source and the drain. The input electrode is formed on the substrate. The carbon nanotube gate is clamped on one end by a contact electrode and positioned, preferably cantilevered, over the gap and over the input electrode.

Abstract: One object of the present invention is reduction of off current of a thin film transistor. Another object of the present invention is improvement of electric characteristics of the thin film transistor. Further, another object of the present invention is improvement of image quality of the display device including the thin film transistor. The thin film transistor includes a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film which is provided over a gate electrode with the gate insulating film interposed therebetween and which is provided in an inner region of the gate electrode so as not to overlap with an end portion of the gate electrode, a film covering at least a side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at.

Abstract: A germanium semiconductor device and a method of manufacturing the same are provided.

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.

Abstract: Methods of constructing silicon carbide semiconductor devices in a self-aligned manner. According to one aspect of the invention, the method may include forming a mesa structure in a multi-layer laminate including at least a first and second layer of silicon carbide material. The mesa structure may then be utilized in combination with at least one planarization step to construct devices in a self-aligned manner. According to another aspect of the present invention, the mesa structure may be formed subsequent to an ion implantation and anneal steps to construct devices in a self-aligned manner. According to another aspect of the present invention, a high temperature mask capable of withstanding the high temperatures of the anneal process may be utilized to form devices in a self-aligned manner.

Abstract: Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Abstract: Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1019 cm?3 or less.

Abstract: It is an object of the present invention to provide a semiconductor device mounted with a memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. It is another object to provide a write-once read-many memory into which data can be written anytime after manufacture of a semiconductor device. An antenna, an antifuse-type ROM, and a driver circuit are formed over a substrate having an insulating surface. A stacked layer of a silicon film and a germanium film is interposed between a pair of electrodes included in the antifuse-type ROM. The antifuse-type ROM having this stacked layer can reduce fluctuation in writing voltage.

Abstract: The present invention relates to a semiconductor structure such as a field effect transistors (FETs) in which the channel region of each of the FETs is composed of an array of more than one electrically isolated channel. In accordance with the present invention, the distance between each of the channels present in the channel region is within a distance of no more than twice their width from each other. The FETs of the present invention are fabricated using methods in which self-assembled block copolymers are employed in forming the channel.