Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.

Abstract: A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.

Abstract: According to one embodiment, a semiconductor substrate includes a cell region and a peripheral circuit region, a first dielectric film is formed on the semiconductor substrate in the cell region and the peripheral circuit region, a first conductive film is formed on the first dielectric film in the cell region and the peripheral circuit region, a first inter-conductive-film dielectric film is formed on the first conductive film in the cell region, a second inter-conductive-film dielectric film is formed on the first conductive film in the peripheral circuit region and a film thickness thereof is larger than the first inter-conductive-film dielectric film, and a second conductive film is formed on the first inter-conductive-film dielectric film in the cell region and the second inter-conductive-film dielectric film in the peripheral circuit region.

Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.

Abstract: A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.

Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.

Abstract: A semiconductor memory has a composite floating structure in which quantum dots composed of Si and coated with a Si oxide thin film are deposited on an insulating film formed on a semiconductor substrate, quantum dots coated with a high-dielectric insulating film are deposited on the quantum dots, and quantum dots composed of Si and coated with a high-dielectric insulating film are further deposited. Each of the quantum dots includes a core layer and a clad layer which covers the core layer. The electron occupied level in the core layer is lower than that in the clad layer.

Abstract: Random number generating element comprises source region, drain region, semiconductor channel provided between source region and drain region and having portion of width W and length L, width W and length L satisfying W?(?/10(?m2))/L, tunnel insulation film provided on semiconductor channel, and conductive fine particle group containing conductive fine particles provided on tunnel insulation film with surface density not less than 2.5×1011 cm?2, charge and discharge of electrons generating between conductive fine particles and semiconductor channel via tunnel insulation film, wherein following inequalities are satisfied: LWDdot?[RTunnel/RTunnel(Tox=0.8 nm)]0.3 nm/T×exp[0.3 nm×(0.8 nm/T)×(4?(2m×3.1 eV)1/2/h)], (q/4??T)?26meV, [Ddot×d4/3/(W×L1/2)]×[RTunnel/RTunnel(Tox=0.8 nm)]?2/3?8000×21/2(?m?13/6) where Ddot represents surface density, d average diameter, T thickness, Rtunnel tunnel resistance per unit area, Rtunnel (Tox=0.8 nm) tunnel resistance, per unit area, of tunnel oxide film with thickness of 0.

Abstract: The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract: A quantum coherent switch having a substrate formed from a density wave (DW) material capable of having a periodic electron density modulation or spin density modulation, a dielectric layer formed onto a surface of the substrate that is orthogonal to an intrinsic wave vector of the DW material; and structure for applying an external spatially periodic electrostatic potential over the dielectric layer.

Abstract: A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the surface of the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. A control gate layer is formed on the inter-gate dielectric layer. After that, the mask layer and the floating gate layer under the mask layer are removed to form another opening. A select gate layer is formed inside the opening.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.