With Schottky Drain Or Source Contact (epo) Patents (Class 257/E29.311)
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Patent number: 9018638Abstract: A MOSFET device is provided. An N-type epitaxial layer is disposed on an N-type substrate. An insulating trench is disposed in the epitaxial layer. A P-type well region is disposed in the epitaxial layer at one side of the insulating trench. An N-type heavily doped region is disposed in the well region. A gate structure is disposed on the epitaxial layer and partially overlaps with the heavily doped region. At least two P-type first doped regions are disposed in the epitaxial layer below the well region. At least one P-type second doped region is disposed in the epitaxial layer and located between the first doped regions. Besides, the first and second doped regions are separated from each other. The first doped regions extend along a first direction, and the second doped region extends along a second direction different from the first direction.Type: GrantFiled: June 11, 2013Date of Patent: April 28, 2015Assignee: Industrial Technology Research InstituteInventors: Chee-Wee Liu, Hui-Hsuan Wang
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Patent number: 8716078Abstract: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.Type: GrantFiled: May 10, 2012Date of Patent: May 6, 2014Assignee: Avogy, Inc.Inventors: Donald R. Disney, Richard J. Brown, Hui Nie
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Patent number: 8658523Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.Type: GrantFiled: September 9, 2010Date of Patent: February 25, 2014Assignee: Acorn Technologies, Inc.Inventors: Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp
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Patent number: 8598636Abstract: The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal.Type: GrantFiled: August 17, 2011Date of Patent: December 3, 2013Assignee: Peking UniversityInventors: Ru Huang, Xin Huang, Shoubin Xue, Yujie Ai
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Publication number: 20130001655Abstract: The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal.Type: ApplicationFiled: August 17, 2011Publication date: January 3, 2013Inventors: Ru Huang, Xin Huang, Shoubin Xue, Yujie Ai
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Patent number: 8338866Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.Type: GrantFiled: November 30, 2011Date of Patent: December 25, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Hisao Kawasaki
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Patent number: 8154025Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.Type: GrantFiled: September 18, 2009Date of Patent: April 10, 2012Assignee: Avolare 2, LLCInventors: John P. Snyder, John M. Larson
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Patent number: 8084793Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.Type: GrantFiled: February 11, 2009Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hisao Kawasaki
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Patent number: 8039902Abstract: Semiconductor devices include a substrate having first and second active regions; a P-channel transistor associated with the first active region and including at least one of source and drain regions; an N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; first and second contact pad layers each including silicon (Si) and SiGe epitaxial layers on the source and drain regions the SiGe epitaxial layers being sequentially stacked on the Si epitaxial layers; an interlayer insulating film; a first metal silicide film on the SiGe epitaxial layer of the P-channel transistor and a second metal silicide film on the Si epitaxial layer of the N-channel transistor; and contact plugs on the first and second metal silicide films.Type: GrantFiled: November 13, 2009Date of Patent: October 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-bum Kim, Si-young Choi, Hyung-ik Lee, Ki-hong Kim, Yong-koo Kyoung
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Publication number: 20110114999Abstract: To provide a deposition technique for forming an oxide semiconductor film. An oxide semiconductor film is formed using a sputtering target which contains a sintered body of metal oxide and in which the concentration of hydrogen contained in the sintered body of metal oxide is, for example, as low as 1×1016 atoms/cm3 or lower, so that the oxide semiconductor film contains a small amount of impurities such as a hydrogen atom and a compound containing a hydrogen atom typified by H2O. Further, this oxide semiconductor film is used as an active layer of a transistor.Type: ApplicationFiled: November 12, 2010Publication date: May 19, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Toru TAKAYAMA, Keiji SATO
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Patent number: 7884002Abstract: A method of fabricating a self-aligned Schottky junction (29) in respect of a semiconductor device. After gate etching and spacer formation, a recess defining the junction regions is formed in the Silicon substrate (10) and a SiGe layer (22) is selectively grown therein. A dielectric layer (24) is then provided over the gate (14) and the SiGe layer (22), a contact etch is performed to form contact holes (26) and the SiGe material (22) is then removed to create cavities (28) in the junction regions. Finally the cavities (28) are filled with metal to form the junction (29). Thus, a process is provided for self-aligned fabrication of a Schottky junction having relatively low resistivity, wherein the shape and position of the junction can be well controlled.Type: GrantFiled: November 27, 2006Date of Patent: February 8, 2011Assignee: NXP B.V.Inventor: Markus Muller
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Publication number: 20110024802Abstract: To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in the first and second regions respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region lying in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; a third semiconductor region formed between adjacent second conductors in the second region, the third semiconductor region having the same conductivity type as that of the second semiconductor region and being lower in density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, the third semiconductor region having a metal contactType: ApplicationFiled: October 11, 2010Publication date: February 3, 2011Inventors: NOBUYUKI SHIRAI, Nobuyoshi Matsuura, Yoshito Nakazawa
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Patent number: 7816240Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.Type: GrantFiled: February 23, 2007Date of Patent: October 19, 2010Assignee: Acorn Technologies, Inc.Inventors: Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp
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Patent number: 7791138Abstract: A semiconductor component and method of making a semiconductor component. One embodiment provides a first metallization structure electrically coupled to charge compensation zones via an ohmic contact and to drift zones via a Schottky contact. A second metallization structure, which is arranged opposite the first metallization structure, is electrically coupled to the charge compensation zones via a Schottky contact and to drift zones via an ohmic contact.Type: GrantFiled: October 30, 2008Date of Patent: September 7, 2010Assignee: Infineon Technologies Austria AGInventor: Frank Pfirsch
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Patent number: 7763938Abstract: A transistor has a source electrode (22) on the opposite side of a semiconductor body layer (10) to a gate electrode (4) insulated from the body layer (10) by gate insulator (8). The source electrode (22) has a potential barrier to the semiconductor body layer (10), for example a Schottky barrier. At least one drain electrode (54) is also connected to the semiconductor body layer (10). A suitable source-drain voltage and gate voltage depletes the region of the semiconductor body layer adjacent to the source electrode (22), and then source-drain current is controlled by the gate voltage.Type: GrantFiled: July 29, 2003Date of Patent: July 27, 2010Assignee: Koninklijke Philips Electronics N.V.Inventors: John M. Shannon, Edmund G. Gerstner
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Publication number: 20090250730Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.Type: ApplicationFiled: February 11, 2009Publication date: October 8, 2009Applicant: Kabushiki Kaisha ToshibaInventor: Hisao KAWASAKI
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Patent number: 7453133Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.Type: GrantFiled: June 30, 2004Date of Patent: November 18, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lee, Chung-Hu Ge, Chenming Hu
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Publication number: 20080191285Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device are reduced by forming the PMOS device over a semiconductor layer having a low valence band.Type: ApplicationFiled: February 9, 2007Publication date: August 14, 2008Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Wen-Chin Lee
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Patent number: 7405449Abstract: A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor comprising a semiconductor region of the first conductivity type including first and second channel regions, gate insulating films provided on the first and second channel regions, a gate electrode provided on the gate insulating films, and first and second source/drain regions which are located at a distance from each other so as to sandwich the first and second channel regions, the first and second source/drain regions contacting the semiconductor region of the first conductivity type and forming a Schottky junction.Type: GrantFiled: September 28, 2005Date of Patent: July 29, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Atsushi Yagishita
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Patent number: 7405452Abstract: A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 ? gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.Type: GrantFiled: February 2, 2004Date of Patent: July 29, 2008Inventor: Hamza Yilmaz