Programmable Transistor (e.g., With Charge-trapping Quantum Well) (epo) Patents (Class 257/E29.316)
-
Patent number: 8536642Abstract: A vertical transistor comprises a semiconductor region, a pillar region formed on the semiconductor region, a gate insulating film formed so as to cover a side surface of the pillar region, a gate electrode formed on the gate insulating film, a first impurity diffusion region formed in an upper portion of the pillar region, and a second impurity diffusion region formed in the semiconductor region so as to surround the pillar region. The first impurity diffusion region is formed so as to be spaced from the side surface of the pillar region.Type: GrantFiled: October 12, 2010Date of Patent: September 17, 2013Assignee: Elpida Memory, Inc.Inventor: Kazuo Ogawa
-
Patent number: 8324681Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.Type: GrantFiled: June 16, 2011Date of Patent: December 4, 2012Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Hang-Ting Lue, Kuang Yeu Hsieh
-
Patent number: 8279904Abstract: A semiconductor light-emitting device including an active layer is provided. The light-emitting device includes an active layer between an n-type semiconductor layer and a p-type semiconductor layer. The active layer includes a quantum well layer formed of Inx1Ga(1?x1)N, where 0<x1?1, barrier layers formed of Inx2Ga(1?x2)N, where 0?x2<1, on opposite surfaces of the quantum well layer, and a diffusion preventing layer formed between the quantum well layer and at least one of the barrier layers. Due to the diffusion preventing layer between the quantum well layer and the barrier layers in the active layer, the light emission efficiency increases.Type: GrantFiled: June 19, 2007Date of Patent: October 2, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Tan Sakong, Joong-kon Son, Ho-sun Paek, Sung-nam Lee
-
Patent number: 7977735Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.Type: GrantFiled: March 3, 2010Date of Patent: July 12, 2011Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Hang-Ting Lue, Kuang Yeu Hsieh
-
Patent number: 7956348Abstract: A quantum device comprises first conductive members and second conductive members confining carriers in the z direction and having two dimensional electron gas on the xy plane. Third conductive members generating an electric field having an effect on the first conductive members. An insulating member easily passing a tunnel current between the first conductive members and the second conductive members. Another insulating member hardly passing a tunnel current between the first conductive members and the third conductive members. An electric field generated by a potential applied to the third conductive members has an effect on the sub-band of the first conductive members.Type: GrantFiled: May 26, 2005Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventor: Yasunao Katayama
-
Patent number: 7879738Abstract: An integrated circuit structure comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of materials between the top and bottom surfaces are non-uniform and arranged to induce a variation in energy gap between the top and bottom surfaces. The variation in energy gap establishes an electric field between the top and bottom surfaces tending to oppose charge motion toward at least one of the top and bottom surfaces and prevent resultant charge leakage.Type: GrantFiled: August 21, 2006Date of Patent: February 1, 2011Assignee: Macronix International Co., Ltd.Inventor: Szu Yu Wang
-
Publication number: 20100213441Abstract: A quantum well (QW) layer is provided in a semiconductive device. The QW layer is provided with a beryllium-doped halo layer in a barrier structure below the QW layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.Type: ApplicationFiled: February 20, 2009Publication date: August 26, 2010Inventors: Ravi Pillarisetty, Titash Rakshit, Mantu Hudait, Marko Radosavljevic, Gilbert Dewey, Benjamin Chu-Kung
-
Patent number: 7709334Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.Type: GrantFiled: June 22, 2006Date of Patent: May 4, 2010Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Hang-Ting Lue, Kuang-Yeu Hsieh
-
Patent number: 7670963Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.Type: GrantFiled: September 26, 2007Date of Patent: March 2, 2010Assignee: Cypress Semiconductor CorportionInventors: Krishnaswamy Ramkumar, Sagy Levy
-
Patent number: 7608883Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.Type: GrantFiled: February 28, 2008Date of Patent: October 27, 2009Assignee: Intel CorporationInventors: Marko Radosavljevic, Amlan Majumdar, Suman Datta, Justin Brask, Brian Doyle, Robert Chau
-
Patent number: 7560335Abstract: Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors.Type: GrantFiled: August 30, 2005Date of Patent: July 14, 2009Assignee: Micron Technology, Inc.Inventor: Seiichi Aritome
-
Publication number: 20070290234Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.Type: ApplicationFiled: June 16, 2006Publication date: December 20, 2007Inventor: Shye-Lin Wu
-
Patent number: 7208753Abstract: A transistor having a bottom dielectric layer, a first layer, a second layer, a top dielectric layer, and a gate electrode. The first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer. The first layer, the second layer, and the top dielectric layer are configured to form a hole wire in the first layer. The gate electrode is over a portion of the hole wire and divides the top dielectric layer into a source contact and a drain contact.Type: GrantFiled: February 24, 2006Date of Patent: April 24, 2007Assignee: The United States of America as represented by the Secretary of the NavyInventors: Ming Yang, Chia-Hung Yang, Yuli Lyanda-Geller