Controllable By Variation Of Magnetic Field Applied To Device (epo) Patents (Class 257/E29.323)
-
Publication number: 20130175644Abstract: A STT-RAM MTJ is disclosed with a composite tunnel barrier comprised of a CoMgO layer that contacts a pinned layer and a MgO layer which contacts a free layer. A CoMg layer with a Co content between 20 and 40 atomic % is deposited on the pinned layer and is then oxidized to produce Co nanoconstrictions within a MgO insulator matrix. The nanoconstrictions control electromigration of Co into an adjoining MgO layer. The free layer may comprise a nanocurrent channel (NCC) layer such as FeSiO or a moment dilution layer such as Ta between two ferromagnetic layers. Furthermore, a second CoMgO layer or a CoMgO/MgO composite may serve as a perpendicular Hk enhancing layer formed between the free layer and a cap layer. One or both of the pinned layer and free layer may exhibit in-plane anisotropy or perpendicular magnetic anisotropy.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: HEADWAY TECHNOLOGIES, INC.Inventors: Cheng T. Horng, Ru-Ying Tong
-
Publication number: 20130175646Abstract: Magnetic structures, methods of forming the same, and memory devices including a magnetic structure, include a magnetic layer, and a stress-inducing layer on a first surface of the magnetic layer, a non-magnetic layer on a second surface of the magnetic layer. The stress-inducing layer is configured to induce a compressive stress in the magnetic layer. The magnetic layer has a lattice structure compressively strained due to the stress-inducing layer.Type: ApplicationFiled: July 16, 2012Publication date: July 11, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-seok Kim, Sung-chul Lee
-
Publication number: 20130168787Abstract: A magnetic sensor suitable for sensing an external magnetic field includes a magnetic tunnel junction (MTJ) device. The MTJ device is used to sense an out-of-plane (Z-axis) component of the external magnetic field at a perpendicular direction to the MTJ device. The MTJ device includes a first pinned magnetic layer, a tunnel layer and a magnetic sensing layer. The first pinned magnetic layer has a pinned magnetization perpendicular to the first pinned magnetic layer. The tunnel layer is disposed on the first pinned magnetic layer. The magnetic sensing layer is disposed on the tunnel layer. The magnetic sensing layer has a critical thickness to be at a superparamagnetic range, in which an out-of-plane (Z-axis) magnetic sensitivity is larger than an in-plane (X-axis, Y-axis) magnetic sensitivity. The first pinned magnetic layer, the tunnel layer and the magnetic sensing layer are stacked in a forward sequence or a reverse sequence.Type: ApplicationFiled: April 20, 2012Publication date: July 4, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Kuei-Hung Shen
-
Publication number: 20130168808Abstract: Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants.Type: ApplicationFiled: December 30, 2011Publication date: July 4, 2013Inventors: Andrei Papou, William French, Peter J. Hopper
-
Publication number: 20130168786Abstract: A magnetic shift register includes a first supporting layer, a second supporting layer, a first pinning material layer, and at least one magnetic memory track. The first supporting layer has trenches on a first surface extending along a first direction. The second supporting layer is filled in the trenches, wherein the first support layer and the second support layer have at least a portion substantially equal in height. The first pinning material layer is disposed between the first supporting layer and the second supporting layer, wherein a plurality of end surfaces of the first pinning material layer are exposed on the first surface. The magnetic memory track extending along a second direction on the first surface is disposed over the first support layer, the first pinning material layer, and the second support layer, wherein the second direction is not the same or perpendicular to the first direction.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: Industrial Technology Research InstituteInventor: Kuei-Hung Shen
-
Patent number: 8477531Abstract: A semiconductor memory device includes a magnetic tunneling junction (MTJ); and a magnetic feature aligned with the MTJ and approximate the MTJ. When viewed in a direction perpendicular to the MTJ and the magnetic feature, the magnetic feature has a disk shape, and the MTJ has an elliptical shape and is positioned within the disk shape.Type: GrantFiled: December 15, 2010Date of Patent: July 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chwen Yu, Tien-Wei Chiang
-
Patent number: 8476722Abstract: A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the first vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer.Type: GrantFiled: April 21, 2011Date of Patent: July 2, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jangeum Lee, Sechung Oh, Jeahyoung Lee, Woojin Kim, Junho Jeong, Woo Chang Lim
-
Publication number: 20130161768Abstract: A magnetic device has a contact structure including a magnetic material therein. The contact structure is magnetostatically and/or electrically coupled to a magnetic element such as one having a magnetic tunneling junction (MTJ) multilayer structure. The magnetic material included in the contact structure is configured to compensate for an offset field acting on the free layer of the magnetic element by reference layers of the magnetic element.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Alexey Vasilyevitch Khvalkovskiy, Vladimir Nikitin, Dmytro Apalkov, Mohamad Towfik Krounbi
-
Publication number: 20130161769Abstract: Magnetoresistive elements, and memory devices including the same, include a free layer having a changeable magnetization direction, a pinned layer facing the free layer and having a fixed magnetization direction, and an auxiliary element on a surface of the pinned layer. The auxiliary element has a width smaller than a width of the pinned layer, and a magnetization direction fixed to a direction the same as a direction of the fixed magnetization direction of the pinned layer.Type: ApplicationFiled: August 22, 2012Publication date: June 27, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-chul LEE, Kwang-seok KIM, Kee-won KIM, Young-man JANG, Ung-hwan PI
-
Publication number: 20130154034Abstract: A method and system for setting the direction of pinned layers in a magnetic junction are described. In one aspect, a magnetic field greater than the coercivity of the layers in a pinned layer but less than the coupling field between the layers is applied. In another aspect the pinned layers are switched from an anti-dual state to a dual state using a spin transfer torque current. In another aspect, a magnetic junction having a partial perpendicular anisotropy (PPMA) layer in the pinned layer is provided. In some aspects, the PPMA layer is part of a synthetic antiferromagnetic structure. In some embodiments, a decoupling layer is provided between the PPMA layer and another ferromagnetic layer in the pinned layer.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dmytro Apalkov, Alexey Vasilyevitch Khvalkovskiy, Vladimir Nikitin, Mohamad Towfik Krounbi, Xueti Tang, Se Chung Oh, Woo Chang Lim, Jang Eun Lee, Ki Woong Kim, Kyoung Sun Kim
-
Patent number: 8466524Abstract: Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment.Type: GrantFiled: March 3, 2011Date of Patent: June 18, 2013Assignee: Seagate Technology LLCInventors: Yuankai Zheng, Xiaohua Lou, Haiwen Xi, Michael Xuefei Tang
-
Publication number: 20130146996Abstract: The present disclosure provides for magnetic devices and methods of fabricating such a device. In one embodiment, a magnetic device includes a first elliptical pillar of first material layers; a second elliptical pillar concentrically disposed over the first elliptical pillar, the second elliptical pillar includes second material layers. The second elliptical pillar is smaller than the first elliptical pillar in size.Type: ApplicationFiled: December 8, 2011Publication date: June 13, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chwen Yu, Tien-Wei Chiang, Kai-Wen Cheng
-
Publication number: 20130146830Abstract: Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.Type: ApplicationFiled: November 5, 2012Publication date: June 13, 2013Inventor: Samsung Electronics Co., Ltd.
-
Publication number: 20130147472Abstract: The cost and size of an atomic magnetometer are reduced by attaching a vapor cell structure that has a vapor cell cavity to a base die that has a laser light source that outputs light to the vapor cell cavity, and attaching a photo detection die that has a photodiode to the vapor cell structure to detect light from the laser light source that passes through the vapor cell cavity.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Inventors: William French, Philipp Lindorfer, Peter J. Hopper, Roozbeh Parsa, Andrew James West, Byron Jon Roderick Shulver
-
Patent number: 8461834Abstract: A magneto-impedance sensor element is formed in a planar type structure in which an amorphous wire is incorporated in a substrate. The magneto-impedance sensor element includes a nonmagnetic substrate, an amorphous wire arranged in an aligning direction of a planar pattern that forms a detecting coil, a spiral detecting coil formed of a planar pattern and a cubic pattern on an outer periphery of the amorphous wire, a planar insulating portion that insulates the planar pattern from the amorphous wire, a wire fixing portion to fix the amorphous wire on an upper surface of the planar insulating portion, and a cubic insulating portion that insulates the cubic pattern from the amorphous wire.Type: GrantFiled: February 27, 2009Date of Patent: June 11, 2013Assignee: Aichi Steel CorporationInventors: Yoshinobu Honkura, Michiharu Yamamoto, Katsuhiko Nishihata
-
Publication number: 20130140657Abstract: Magnetic memory devices including a free magnetic layer having a three-dimensional structure, include a switching device and a magnetic tunnel junction (MTJ) cell connected thereto. The MTJ cell includes a lower magnetic layer, a tunnel barrier layer, and a free magnetic layer, which are sequentially stacked. A portion of the free magnetic layer protrudes in a direction away from an upper surface of the tunnel barrier layer.Type: ApplicationFiled: August 10, 2012Publication date: June 6, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-chul LEE, Kwang-seok KIM, Kee-won KIM, Young-man JANG, Ung-hwan PI
-
Patent number: 8455967Abstract: There is disclosed a memory element including a layered structure including a memory layer that has magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer. An electron that is spin-polarized is injected in a lamination direction of the layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed with respect to the memory layer, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and the memory layer and the magnetization-fixed layer have a film thickness in such a manner that an interface magnetic anisotropy energy becomes larger than a diamagnetic energy.Type: GrantFiled: August 24, 2011Date of Patent: June 4, 2013Assignee: Sony CorporationInventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Kazutaka Yamane, Hiroyuki Uchida
-
Patent number: 8455962Abstract: A magneto-impedance sensor element has a base body, a magnetic amorphous wire, a coating insulator, a detecting coil, a terminal base having a terminal mounting surface, wire electrode terminals and coil electrode terminals formed on the terminal mounting surface, wire connecting wirings for electrically connecting the wire electrode terminals and a pair of wire conducting terminals provided to the magnetic amorphous wire, and coil connecting wirings for electrically connecting the coil electrode terminals and a pair of coil conducting terminals provided to the detecting coil. A normal of the terminal mounting surface has a longitudinal direction component of the magnetic amorphous wire, and the terminal mounting surface is arranged between both ends of the magnetic amorphous wire in the longitudinal direction of the magnetic amorphous wire.Type: GrantFiled: June 9, 2009Date of Patent: June 4, 2013Assignee: Aichi Steel CorporationInventors: Yoshinobu Honkura, Michiharu Yamamoto, Katsuhiko Nishihata
-
Patent number: 8455966Abstract: Provided are transistor devices such as logic gates that are capable of associating a computational state and or performing logic operations with detectable electronic spin state and or magnetic state. Methods of operating transistor devices employing magnetic states are provided. Devices comprise input and output structures and magnetic films capable of being converted between magnetic states.Type: GrantFiled: December 23, 2010Date of Patent: June 4, 2013Assignee: Intel CorporationInventors: C Michael Garner, Dmitri E. Nikonov
-
Publication number: 20130126996Abstract: A magnetic memory device using magnetic resistance is provided. The magnetic memory device may include a magnetic memory layer comprising a plurality of magnetic layers; and a tunnel barrier layer provided between the plurality of magnetic layers; and a stress-generating layer for applying stress to the tunnel barrier layer.Type: ApplicationFiled: July 14, 2012Publication date: May 23, 2013Inventor: Dae-eun Jeong
-
Publication number: 20130126995Abstract: According to one embodiment, a semiconductor substrate device includes a plurality of memory elements formed on the top surface of a semiconductor substrate, interlayer insulating films buried between the adjacent memory elements, a protection film formed on sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements, and contacts formed in the interlayer insulating films. The protection film includes a first protection film formed on the sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements and a second protection film formed on the first protection film. The first protection film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, and the second protection film is made of a boron film or a boron nitride film.Type: ApplicationFiled: March 14, 2012Publication date: May 23, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hirotaka Ogihara
-
Patent number: 8445980Abstract: There is disclosed a memory element which includes a layered structure. The layered structure includes a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer having magnetization perpendicular to the film face; an insulating layer provided between the memory layer and the magnetization-fixed layer; and a cap layer provided at a face side, which is opposite to the insulating layer-side face, of the memory layer, in which an electron that is spin-polarized is injected in a lamination direction of the layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and at least a face, which comes into contact with the memory layer, of the cap layer is formed of a Ta film.Type: GrantFiled: August 24, 2011Date of Patent: May 21, 2013Assignee: Sony CorporationInventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Kazutaka Yamane, Hiroyuki Uchida
-
Patent number: 8445979Abstract: A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier. A second junction magnetic layer may be on the tunnel barrier with the tunnel barrier being between the first and second junction magnetic layers, and a second vertical magnetic layer may be on the second junction magnetic layer with the second junction magnetic layer being between the tunnel barrier and the second vertical magnetic layer.Type: GrantFiled: August 24, 2010Date of Patent: May 21, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sechung Oh, Jangeun Lee, Jeahyoung Lee, Woojin Kim, Woo Chang Lim, Junho Jeong, Sukhun Choi
-
Publication number: 20130119495Abstract: Semiconductor stack structures such as magnetic tunnel junction structures having a magnetic free layer that is grown on composite, obliquely deposited seed layers to induce an increased in-plane magnetic anisotropy Hk of the magnetic free layer. In one aspect, a semiconductor device includes a composite seed layer formed on a substrate, and a magnetic layer formed on the composite seed layer. The composite seed layer includes a first seed layer obliquely formed with an incident angle from a surface normal of the substrate along a first direction of the substrate, and a second seed layer obliquely formed with the incident angle on the first seed layer along a second direction of the substrate, opposite the first direction.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: International Business Machines CorporationInventors: Francesco A. Vetrò, Daniel C. Worledge
-
Publication number: 20130119496Abstract: The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer.Type: ApplicationFiled: October 17, 2012Publication date: May 16, 2013Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI)Inventors: SEMICONDUCTOR MANUFACTURING INTERNA, SEMICONDUCTOR MANUFACTURING INTERNA
-
Patent number: 8441083Abstract: To provide a semiconductor device that has an improved adhesion between a bottom conductive layer and a protection film protecting an MTJ element. This semiconductor device includes a bottom electrode formed over a semiconductor substrate, an MTJ element part formed over a part of the bottom electrode by lamination of a bottom magnetic film, an insulating film, a top magnetic film, and a top electrode in this order, and a protection film formed over the bottom electrode so as to cover the MTJ element part, wherein the bottom electrode is formed by amorphized metal nitride and the protection film is formed by an insulating film containing nitrogen.Type: GrantFiled: April 30, 2012Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventors: Keisuke Tsukamoto, Mikio Tsujiuchi
-
Patent number: 8441082Abstract: There is provided a memory element including a magnetic layer that includes FexNiyBz (here, x+y+z=1, 0.2x?y?4x, and 0.1(x+y)?z?0.4(x+y)) as a main component, and has magnetic anisotropy in a direction perpendicular to a film face; and an oxide layer that is formed of an oxide having a sodium chloride structure or a spinel structure and comes into contact with one face of the magnetic layer.Type: GrantFiled: September 6, 2011Date of Patent: May 14, 2013Assignee: Sony CorporationInventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
-
Publication number: 20130114336Abstract: A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process.Type: ApplicationFiled: January 24, 2012Publication date: May 9, 2013Applicant: QUALCOMM IncorporatedInventors: Xia Li, Xiaochun Zhu, Seung H. Kang, Jung Pill Kim, Wah Nam Hsu, Taehyun Kim, Kangho Lee
-
Patent number: 8436437Abstract: A STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and a free layer that comprises an amorphous layer of Co60Fe20B20 of approximately 20 angstroms thickness or an amorphous ferromagnetic layer of Co40Fe40B20 of approximately 15 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.Type: GrantFiled: June 21, 2010Date of Patent: May 7, 2013Assignee: MagIC Technologies, Inc.Inventors: Cheng T. Horng, Ru-Ying Tong, Chyu-Jiuh Torng, Witold Kula
-
Patent number: 8435653Abstract: A spin transport element 1 has a first ferromagnet 12A, a second ferromagnet 12B, a channel 7 extending from the first ferromagnet 12A to the second ferromagnet 12B, a magnetic shield S1 covering the channel 7, and an insulating film provided between the channel 7 and the magnetic shield S1.Type: GrantFiled: March 10, 2011Date of Patent: May 7, 2013Assignee: TDK CorporationInventor: Tomoyuki Sasaki
-
Patent number: 8436438Abstract: There is provided a memory element including a memory layer that has magnetization perpendicular to a film face; a magnetization-fixed layer that has magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, the insulating layer is formed of an oxide film, and the memory layer is formed of Co—Fe—B, a concentration of B is low in the vicinity of an interface with the insulating layer, and the concentration of B increases as it recedes from the insulating layer.Type: GrantFiled: August 24, 2011Date of Patent: May 7, 2013Assignee: Sony CorporationInventors: Kazuhiro Bessho, Masanori Hosomi, Hiroyuki Ohmori, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
-
Publication number: 20130099337Abstract: According to one embodiment, a magnetic memory element includes a memory layer, a first nonmagnetic layer, a reference layer, a second nonmagnetic layer, and an adjustment layer which are stacked. The adjustment layer is configured to reduce a leakage magnetic field from the reference layer. The adjustment layer is formed by stacking an interface layer provided on the second nonmagnetic layer, and a magnetic layer having magnetic anisotropy perpendicular to a film surface. Saturation magnetization of the interface layer is larger than that of the magnetic layer.Type: ApplicationFiled: September 5, 2012Publication date: April 25, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Masahiko Nakayama, Hisanori Aikawa, Masaru Toko, Hiroaki Yoda, Tatsuya Kishi, Sumio Ikegawa
-
Publication number: 20130099334Abstract: A z-axis fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence forms a vertical magnetic core structure, a first wire structure wound around the magnetic core structure, and a second wire structure wound around the magnetic core structure.Type: ApplicationFiled: October 19, 2011Publication date: April 25, 2013Inventors: Anuraag Mohan, Peter J. Hopper
-
Publication number: 20130099336Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.Type: ApplicationFiled: March 22, 2012Publication date: April 25, 2013Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventors: Chi Min-Hwa, Mieno Fumitake
-
Publication number: 20130099335Abstract: Using a damascene process, a cup-shaped MTJ device is formed in an opening within a dielectric layer. A passivation layer is formed on the top surfaces of the sidewalls of the cup-shaped MTJ device to enclose the top of the sidewalls, thereby reducing magnetic flux leakage. Accordingly, the MTJ device may be fabricated using the same equipment that are compatible with and commonly used in CMOS technologies/processes.Type: ApplicationFiled: December 22, 2011Publication date: April 25, 2013Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Min-Hwa Chi, Xiufeng Han, Guoqiang Yu
-
Publication number: 20130099338Abstract: According to one embodiment, a magnetic memory element includes a memory layer having magnetic anisotropy perpendicular to a film surface and having a variable magnetization direction, a first nonmagnetic layer provided on the memory layer, and a reference layer provided on the first nonmagnetic layer, having magnetic anisotropy perpendicular to a film surface, and having an invariable magnetization direction. An area of the memory layer is larger than that of the reference layer. Magnetization in an end portion of the memory layer is smaller than that in a central portion of the memory layer.Type: ApplicationFiled: September 5, 2012Publication date: April 25, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masahiko Nakayama, Tatsuya Kishi, Hiroaki Yoda, Hisanori Aikawa, Masaru Toko
-
Publication number: 20130099339Abstract: A spintronic electronic apparatus having a multilayer structure. The apparatus includes a substrate, having disposed in succession upon the substrate; a bottom interface layer; a pinned layer; a tunneling barrier; a free layer; and a top interface layer, wherein the apparatus operates as a non-resonant magnetic tunnel junction in a large amplitude, out-of-plane magnetization precession regime having weakly current dependent, large diode volt-watt sensitivity when external microwave signals that exceed a predetermined threshold current and have a frequency that is lower than a predetermined level excite the magnetization precession.Type: ApplicationFiled: October 20, 2011Publication date: April 25, 2013Applicant: The United States of America as Represented by the Secretary of the ArmyInventors: Thomas J. Meitzler, Elena N. Bankowski, Michael Nranian, Ilya N. Krivorotov, Andrei N. Slavin, Vasyl S. Tyberkevych
-
Patent number: 8426935Abstract: Provided are an electronic device, a memory device, and a method of fabricating the devices for preventing physical distortion of functional elements from generating and improving electric contact properties between the functional elements and electric elements connecting to the functional elements. At least two grooves are formed in a substrate, and a conductive material is filled in the grooves to obtain electric elements having a surface at the same height as that of the substrate. In addition, a functional material layer (functional layer) is formed on an entire upper surface of the substrate and is patterned so as to obtain a functional element having both bottom surfaces contacting the electric elements.Type: GrantFiled: February 4, 2010Date of Patent: April 23, 2013Assignee: Korea University Research and Business FoundationInventors: Gyu Tae Kim, Kang Ho Lee, Hye Young Kim, Kyung Jin Lee, Woun Kang
-
Publication number: 20130094280Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.Type: ApplicationFiled: October 15, 2012Publication date: April 18, 2013Applicant: Zeno Semiconductor, Inc.Inventor: Yuniarto Widjaja
-
Publication number: 20130093032Abstract: Semiconductor trench inductor and transformer structures are provided, which include thin film conductive layers and magnetic layers formed within trenches etched in semiconductor substrates. Semiconductor trench devices effectively provide vertical oriented inductor and transformer structures whereby conductive coils and magnetic layers are vertically oriented on edge within trenches, thereby providing a space-saving compact design, and which allows the conductive layers within the trench to be enclosed by magnetic material, thereby providing a density of magnetic material that increases the storable energy density.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: International Business Machines CorporationInventor: Bucknell C. Webb
-
Patent number: 8421138Abstract: A magnetic pinned layer is formed over a substrate. An insulating film is formed over the magnetic pinned layer. A recess is formed in and through the insulating film. A tunneling insulating film is formed over a bottom of the recess. A first magnetic free layer is formed over the bottom of the recess via the tunneling insulating film. A second magnetic free layer is formed over the insulating film and made of a same material as the first magnetic free layer. A non-magnetic film is formed on sidewalls of the recess, extending from the first magnetic free layer to the second magnetic free layer and made of oxide of the material of the first magnetic free layer. An upper electrode is disposed over the first magnetic free layer, non-magnetic film and second magnetic free layer, and electrically connected to the first magnetic free layer and second magnetic free layer.Type: GrantFiled: April 19, 2011Date of Patent: April 16, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Yoshihisa Iba
-
Patent number: 8421171Abstract: A magnetic random access memory (MRAM) has a perpendicular magnetization direction. The MRAM includes a first magnetic layer, a second magnetic layer, a first polarization enhancement layer, a second polarization enhancement layer, a barrier layer, a spacer, and a free assisting layer. A pinned layer formed by the first magnetic layer and the first polarization enhancement layer has a first magnetization direction and a first perpendicular magnetic anisotropy. A free layer formed by the second magnetic layer and the second polarization enhancement layer has a second magnetization direction and a second perpendicular magnetic anisotropy. The barrier layer is disposed between the first polarization enhancement layer and the second polarization enhancement layer. The spacer is disposed on the second magnetic layer. The free assisting layer is disposed on the spacer and has an in-plane magnetic anisotropy. The spacer and the barrier layer are on opposite sides of the free layer.Type: GrantFiled: December 6, 2010Date of Patent: April 16, 2013Assignee: Industrial Technology Research InstituteInventors: Cheng-Tyng Yen, Yung-Hung Wang
-
Patent number: 8421060Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.Type: GrantFiled: January 8, 2010Date of Patent: April 16, 2013Assignee: Korea Institute of Science and TechnologyInventors: Hyun Cheol Koo, Suk Hee Han, Joon Yeon Chang, Hyung Jun Kim, Jang Hae Ku
-
Publication number: 20130087868Abstract: Embodiments relate to Hall-controlled switch devices. In an embodiment, a Hall switch and a load switch are integrated in a single integrated circuit device. Embodiments can provide load switching and optional simultaneous logic signaling, for example to update a microcontroller or electronic control unit (ECU), while reducing space and complexity and thereby cost.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Inventors: Sebastian Maerz, Jean-Marie Le Gall
-
Publication number: 20130087869Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.Type: ApplicationFiled: May 18, 2012Publication date: April 11, 2013Applicant: AVALANCHE TECHNOLOGY, INC.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
-
Publication number: 20130088914Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.Type: ApplicationFiled: May 18, 2012Publication date: April 11, 2013Applicant: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
-
Publication number: 20130087870Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.Type: ApplicationFiled: May 21, 2012Publication date: April 11, 2013Applicant: AVALANCHE TECHNOLOGY, INC.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
-
Publication number: 20130087872Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.Type: ApplicationFiled: May 21, 2012Publication date: April 11, 2013Applicant: AVALANCHE TECHNOLOGY, INC.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
-
Publication number: 20130088915Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.Type: ApplicationFiled: May 18, 2012Publication date: April 11, 2013Applicant: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
-
Publication number: 20130087871Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.Type: ApplicationFiled: May 21, 2012Publication date: April 11, 2013Applicant: AVALANCHE TECHNOLOGY, INC.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall