Capacitor With Potential Barrier Or Surface Barrier (epo) Patents (Class 257/E29.342)
E Subclasses
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Publication number: 20120293208Abstract: As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a plurality of capacitors. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Inventor: Kiyoshi Kato
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Publication number: 20120292681Abstract: A semiconductor device includes a substrate having a groove in a periphery, a gate electrode partially embedded in the groove to sandwich the substrate from opposite directions by side walls of the groove, and a diffusion layer formed over the substrate and surrounded by the gate electrode. A resistance value of the diffusion layer is changed by changing a potential between the gate electrode and the diffusion layer.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Inventors: Yoshinori IKEBUCHI, Yoshihiro TAKAISHI
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Publication number: 20120280359Abstract: Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.Type: ApplicationFiled: July 18, 2012Publication date: November 8, 2012Inventors: Ayako INOUE, Naoto SAITOH
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Patent number: 8304899Abstract: A recessed portion is provided in first and second insulating films, the first insulating film being stacked on a semiconductor wafer, the second insulating film being stacked on the first insulating film. The first and second insulating films are processed to form wiring in a formation region of the semiconductor wafer in which an acceleration sensor is to be formed. After a sacrificial film is stacked on the wiring and processed, a conductive film is stacked on the wiring and processed to form a plurality of thin film structures in the formation region. The recessed portion surrounds the formation region.Type: GrantFiled: July 14, 2008Date of Patent: November 6, 2012Assignee: Mitsubishi Electric CorporationInventors: Mika Okumura, Makio Horikawa, Kimitoshi Satou, Yasuo Yamaguchi
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Patent number: 8304855Abstract: Semiconductor devices (100) and methods of making the same. Each of the semiconductor devices includes a substrate (102) having a first surface (118) and an opposing second surface. A vertical capacitive element (104) is disposed on the first surface of the substrate. The vertical capacitive element comprises a plurality of parallel conductive plates (120b, 120d, 120f, 120h, 120j, 120l, 120n) extending transverse to the first surface of the substrate. Adjacent conductive plates are spaced a distance D from each other. A dielectric material (104) can be disposed in a space separating the adjacent conductive plates. Each of the conductive plates has a height-to-width (h/w) ratio greater than or equal to one.Type: GrantFiled: August 4, 2010Date of Patent: November 6, 2012Assignee: Harris CorporationInventor: David M. Smith
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Publication number: 20120273922Abstract: An amorphous carbon film and an interlayer insulation film are formed in a memory cell region and a peripheral circuit region, respectively. An insulating film is formed on the amorphous carbon film and the interlayer insulation film. A portion of the insulating film that corresponds to capacitors on the amorphous carbon film is removed so that lower electrodes of the capacitors are supported from opposite sides of the lower electrodes. An insulating film pattern continuously extends from the memory cell region to the peripheral circuit region wholly covered with the insulating film pattern. Subsequently, the amorphous carbon film is removed to leave the capacitors supported by the insulating film pattern on both sides of the lower electrodes.Type: ApplicationFiled: April 25, 2012Publication date: November 1, 2012Applicant: ELPIDA MEMORY, INC.Inventor: YASUHIKO UEDA
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Patent number: 8299573Abstract: A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.Type: GrantFiled: June 18, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Chengwen Pei, Xi Li, Geng Wang
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Publication number: 20120267761Abstract: A capacitor is provided. The capacitor includes first and second electrode layers facing each other, a first conductive pattern disposed between the first and second electrode layers, the first conductive pattern forming a closed loop in plan view, a second conductive pattern disposed within an inner space surrounded by the closed loop of the first conductive pattern, the second conductive pattern being spaced from the first conductive pattern, and a first contact plug passing through the second conductive pattern to contact the first and second electrode layers.Type: ApplicationFiled: March 21, 2012Publication date: October 25, 2012Applicants: Korea Advanced Institute of Science and Technology, Electronics and Telecommunications Research InstituteInventors: Chang Sun Kim, Seong Hoon Choi, Jang Hyun Park, Seung-Tak Ryu, Ba-Ro-Saim Sung, Dong-Shin Jo
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Publication number: 20120261798Abstract: A semiconductor device includes a wiring configured to be formed in a surface portion of a first interlayer insulating layer in a first region, a common upper electrode configured to be formed in a surface portion of the first interlayer insulating layer in a second region, a plurality of capacitance portions configured to have the common upper electrode as an upper electrode and be extended below, wherein an upper surface of the first interlayer insulating layer and an upper surface of the common upper electrode approximately lie in the same plane.Type: ApplicationFiled: June 22, 2012Publication date: October 18, 2012Applicant: Renesas Electronics CorporationInventor: Ken Inoue
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Publication number: 20120261797Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.Type: ApplicationFiled: June 22, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph ERVIN, Brian MESSENGER, Karen A. NUMMY, Ravi M. TODI
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Publication number: 20120256193Abstract: A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output power device and electrically coupled to the low-side output power device. A dielectric layer is over a portion of the first metal layer and a portion of the second metal layer, and a top metal layer is over the dielectric layer.Type: ApplicationFiled: June 21, 2011Publication date: October 11, 2012Applicant: INTERSIL AMERICAS INC.Inventors: Francois Hebert, Stephen J. Gaul, Shea Petricek
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Publication number: 20120248434Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.Type: ApplicationFiled: March 21, 2012Publication date: October 4, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kiyoshi KATO, Toshihiko SAITO
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Publication number: 20120241907Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.Type: ApplicationFiled: May 31, 2012Publication date: September 27, 2012Applicant: Texas Instruments IncorporatedInventors: RAJNI J. AGGARWAL, SCOTT R. SUMMERFELT, GUL B. BASIM, TED S. MOISE
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Publication number: 20120241865Abstract: One aspect of the present invention provides an integrated circuit structure including a semiconductor substrate, a bottom dielectric layer positioned on the substrate, at least two capping dielectric layers positioned on the bottom dielectric layer, and a metal layer positioned on the at least two capping dielectric layers, wherein one of the two capping dielectric layers is an aluminum oxide layer, and the other is a silicon oxide layer. Another aspect of the present invention provides an integrated circuit structure including a bottom electrode, a bottom dielectric layer positioned on the bottom electrode, at least two capping dielectric layers positioned on the bottom dielectric layer, and a top electrode positioned on the at least two capping dielectric layers, wherein one of the two capping dielectric layers is an aluminum oxide layer, and the other is a silicon oxide layer.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Vassil Antonov, Vishwanath Bhat, Noel Rocklein, Chris Carlson
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Publication number: 20120241908Abstract: A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.Type: ApplicationFiled: June 5, 2012Publication date: September 27, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Jung-Chih TSAO, Yu-Sheng WANG, Kei-Wei CHEN, Ying-Lang WANG
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Publication number: 20120241909Abstract: A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.Type: ApplicationFiled: March 23, 2011Publication date: September 27, 2012Inventors: Tushar P. Merchant, Michael A. Sadd
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Publication number: 20120241906Abstract: An object of the present invention is to provide a capacitor-incorporated wiring substrate in which connection reliability can be improved through ensuring of a path for supply of electric potential even upon occurrence of a faulty connection in a via-conductor group. In a capacitor-incorporated wiring substrate of the present invention, a capacitor 50 is accommodated in a core 11, and a first and a second buildup layers 12 and 13 are formed on the upper and lower sides, respectively, of the capacitor 50. The capacitor-incorporated wiring substrate has a first via-conductor group to be connected to a first electric potential, and a second via-conductor group to be connected to a second electric potential. A first electrode pattern connected to the first via-conductor group, and a plurality of second electrode patterns connected to the second via-conductor group, are formed in a front-surface electrode layer 51 of the capacitor 50.Type: ApplicationFiled: August 4, 2010Publication date: September 27, 2012Applicant: NGK SPARK PLUG CO., LTD.Inventor: Naoya Nakanishi
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Publication number: 20120235278Abstract: Adhesive strength between a rewiring and a solder bump is improved in a semiconductor integrated circuit device in which a bump electrode is connected to a land section of the rewiring. The land section 20A of the rewiring 20 is formed by a five-layer metal film (a barrier metal film 13, a seed film 14, a Cu film 15, a first Ni film 16, and a second Ni film 17) constituting the rewiring 20, the uppermost-layer second Ni film 17 has a larger area than that of the other metal films (the barrier metal film 13, the seed film 14, the Cu film 15, and the first Ni film 16). A solder bump 21 is connected to the surface of the second Ni film 17. At the end portion of the solder bump 21, a polyimide resin film 22 is formed directly under the second Ni film 17.Type: ApplicationFiled: February 27, 2012Publication date: September 20, 2012Inventors: Hisao Shigihara, Hiromi Shigihara, Akira Yajima
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Publication number: 20120228737Abstract: A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Inventor: Hiroshi FURUTA
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Publication number: 20120228739Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.Type: ApplicationFiled: May 24, 2012Publication date: September 13, 2012Applicant: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Scott R. Summerfelt, Ted S. Moise, Manoj K. Jain
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Patent number: 8263454Abstract: An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed.Type: GrantFiled: August 4, 2010Date of Patent: September 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Se-young Lee, Il-young Yoon, Boung-ju Lee
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Patent number: 8258600Abstract: A semiconductor device includes a capacitor element including a first comb-shaped interconnection formed over a substrate and including a first comb tooth, a second comb-shaped interconnection formed over the substrate and including a second comb tooth opposed to the first comb tooth, and a first electrode and a second electrode opposed to each other with opposed surfaces of the first electrode and the second electrode intersecting a longitudinal direction of the first comb tooth and the second comb tooth, a first dielectric layer formed between the first electrode and the second electrode, the first electrode being connected to the first comb tooth, and the second electrode being connected to the second comb tooth.Type: GrantFiled: March 9, 2010Date of Patent: September 4, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Tsuyoshi Sugisaki, Hajime Kurata
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Publication number: 20120217615Abstract: A grain boundary-insulated semiconductor ceramic contains a SrTiO3-based compound as a main component, and a diffusing agent containing a grain boundary insulating agent and a glass component. The grain boundary insulating agent is composed of a material free of lead, the glass component mainly contains a SiO2—X2O-MO—TiO2-based glass material that does not contain boron or lead and in which X represents an alkali metal, and M represents at least one of barium, strontium, and calcium, and the content of the glass component is 3 to 15 parts by weight relative to 100 parts by weight of the grain boundary insulating agent. A component base is composed of the grain boundary-insulated semiconductor ceramic.Type: ApplicationFiled: January 26, 2012Publication date: August 30, 2012Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Tsutomu Tatekawa
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Publication number: 20120211814Abstract: Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced.Type: ApplicationFiled: April 25, 2012Publication date: August 23, 2012Applicant: International Business Machines CorporationInventor: Kangguo Cheng
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Publication number: 20120205779Abstract: Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided.Type: ApplicationFiled: December 27, 2011Publication date: August 16, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jun Ki KIM
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Publication number: 20120199944Abstract: Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material. Capacitors, semiconductor devices and methods of forming a semiconductor device including the capacitors are also disclosed.Type: ApplicationFiled: February 7, 2011Publication date: August 9, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chun-I Hsieh, Chris Carlson
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Publication number: 20120199947Abstract: A method for manufacturing a TiN/Ta2O5/TiN capacitor, including the steps of forming a Ta2O5 layer on a TiN support by a plasma-enhanced atomic layer deposition method, or PEALD; and submitting the obtained structure to an N2O plasma for a duration sufficient to oxidize the Ta2O5 layer without oxidizing the TiN support.Type: ApplicationFiled: February 2, 2012Publication date: August 9, 2012Applicant: STMicroelectronics (Crolles 2) SASInventor: Mickael Gros-Jean
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Publication number: 20120199949Abstract: Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.Type: ApplicationFiled: February 4, 2011Publication date: August 9, 2012Applicant: QUALCOMM INCORPORATEDInventors: Je-Hsiung Lan, Matthew Michael Nowak, Evgeni P. Gousev, Jonghae Kim, Clarence Chui
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Publication number: 20120199945Abstract: Aspects of the invention provide for methods of forming a deep trench capacitor structure. In one embodiment, aspects of the invention include a method of forming a deep trench capacitor structure, including: forming a deep trench within a semiconductor substrate; depositing a first liner within the deep trench; filling a lower portion of the deep trench with a filler material; depositing a second liner within an upper portion of the deep trench; removing the filler material, such that the lower portion of the deep trench includes only the first liner and the upper portion of the deep trench includes the first liner and the second liner; forming a high doped region around the lower portion of the deep trench; and removing the first liner within the lower portion of the deep trench and the second liner within the upper portion of the deep trench.Type: ApplicationFiled: February 8, 2011Publication date: August 9, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph E. Ervin, Yanli Zhang
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Publication number: 20120193756Abstract: In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.Type: ApplicationFiled: February 2, 2011Publication date: August 2, 2012Inventors: Steven Maxwell, Abhijit Bandyopadhyay, Kun Hou, Er-Xuan Ping, Yung-Tin Chen, Li Xiao
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Publication number: 20120193632Abstract: Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.Type: ApplicationFiled: January 24, 2012Publication date: August 2, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Satoshi TORIUMI
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Publication number: 20120193761Abstract: A capacitor of semiconductor device is provided including a lower electrode on a semiconductor substrate; a dielectric film covering a surface of the lower electrode; and an upper electrode covering the dielectric film. The lower electrode includes a first conductive pattern having a groove region defined by a bottom portion and a sidewall portion; and a first core support pattern disposed in the groove region of the first conductive pattern and exposing a portion of inner sidewall of the first conductive pattern. Related methods are also provided herein.Type: ApplicationFiled: January 30, 2012Publication date: August 2, 2012Inventors: Dongkyun Park, Mansug Kang
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Publication number: 20120187535Abstract: A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.Type: ApplicationFiled: January 10, 2012Publication date: July 26, 2012Applicant: Hynix Semiconductor Inc.Inventor: Un Hee LEE
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Publication number: 20120187537Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.Type: ApplicationFiled: March 30, 2012Publication date: July 26, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Toshiyuki HIROTA
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Publication number: 20120187533Abstract: Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of upwardly-extending sidewalls. Individual sidewalls may have a narrower segment over a wider segment. Capacitor dielectric material and capacitor electrode material may be along the narrower and wider segments of the sidewalls. Some embodiments include methods of forming capacitors in which an initial container-shaped storage node structure is formed to have a pair of upwardly-extending sidewalls along a cross-section, with the sidewalls being of thickness that is substantially constant or increasing from a base to a top of the initial structure. The initial structure is then converted into a modified storage node structure by reducing thicknesses of upper segments of the sidewalls while leaving thicknesses of lower segments of the sidewalls substantially unchanged.Type: ApplicationFiled: January 20, 2011Publication date: July 26, 2012Applicant: Micron Technology, Inc.Inventors: Duane M. Goodner, Sanjeev Sapra, Darwin Franseda Fan
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Patent number: 8227847Abstract: The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (930,950) separated by a dielectric layer (940). Via connections (920) are provided in trenches that go through the whole thickness of the wafer.Type: GrantFiled: February 17, 2009Date of Patent: July 24, 2012Assignee: NXP B.V.Inventors: Francois Neuilly, Francois Le Cornec
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Publication number: 20120181656Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Inventors: Wolfgang Lehnert, Michael Stadtmueller, Stefan Pompl, Markus Meyer
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Publication number: 20120181660Abstract: A semiconductor device comprises a capacitor, the capacitor including a lower electrode, a dielectric film containing crystalline zirconium oxide formed on the lower electrode, and an upper electrode containing a titanium nitride film contacting to the dielectric film, wherein the dielectric film comprises an amorphous film on an interface with the titanium nitride film, thereby preventing the reduction of the thickness of the titanium nitride film formed on the dielectric electrode with a low leakage current and a high dielectric constant.Type: ApplicationFiled: January 13, 2012Publication date: July 19, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Naonori FUJIWARA
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Publication number: 20120181658Abstract: A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape.Type: ApplicationFiled: July 14, 2011Publication date: July 19, 2012Applicant: TESSERA RESEARCH LLCInventors: Ilyas Mohammed, Belgacem Haba, Cyprian Uzoh, Piyush Savalia, Vage Oganesian
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Publication number: 20120175735Abstract: A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.Type: ApplicationFiled: March 18, 2012Publication date: July 12, 2012Applicant: STATS CHIPPAC, LTD.Inventor: Yaojian Lin
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Publication number: 20120175692Abstract: A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; and forming storage node contact lines which fill the second damascene trenches.Type: ApplicationFiled: March 19, 2012Publication date: July 12, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Chun Soo Kang
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Patent number: 8217493Abstract: A semiconductor device includes a plurality of capacitor cells having respective lower electrodes to which signals are applied and respective upper electrodes arranged to face the respective lower electrodes, wherein each interconnect connected to a corresponding one of the lower electrodes includes a shield interconnect section enclosing a corresponding one of the upper electrodes.Type: GrantFiled: June 13, 2008Date of Patent: July 10, 2012Assignee: Mitsumi Electric Co., Ltd.Inventors: Fumihiro Inoue, Hitoshi Shima
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Patent number: 8217475Abstract: Described herein is the sense element assembly for a capacitive pressure sensor and method for creating same that has increased sensitivity despite the parasitic capacitance that is created. The capacitive sensor element assembly, comprises a first semiconductive layer, and a first conductive layer, a first dielectric layer into which a cavity has been formed, the dielectric layer lying between the first semiconductive layer and the first conductive layer, wherein an electrical connection is made to the second conductive layer. A preferred method for fabricating a capacitive sensor assembly of the present invention comprises the steps of forming a dielectric layer on top of a conductive handle wafer; creating at least one cavity in the dielectric layer, bonding a thin semiconductive layer to the dielectric layer and connecting an operational amplifier to the input of the capacitive sensor assembly to overcome the parasitic capacitance formed during fabrication.Type: GrantFiled: May 15, 2008Date of Patent: July 10, 2012Assignee: Custom Sensors & Technologies, Inc.Inventors: Peter Seesink, Omar Abed
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Publication number: 20120168904Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
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Publication number: 20120168905Abstract: The capacitor of a nonvolatile memory device includes first and second electrodes formed in the capacitor region of a semiconductor substrate to respectively have consecutive concave and convex shape of side surfaces formed along each other and a dielectric layer formed between the first and the second electrodes.Type: ApplicationFiled: November 3, 2011Publication date: July 5, 2012Inventor: Je Il RYU
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Publication number: 20120161281Abstract: A method of manufacturing a semiconductor device includes: forming a core insulating film that includes first openings, on a semiconductor substrate; forming cylindrical lower electrodes that cover sides of the first openings with a conductive film; forming a support film that covers at least an upper surface of the core insulating film between the lower electrodes; forming a mask film in which an outside of a region where at least the lower electrodes are formed is removed, by using the support film; and performing isotropic etching on the core insulating film so as to leave the core insulating film at a part of an area between the lower electrodes, after the mask film is formed.Type: ApplicationFiled: December 28, 2011Publication date: June 28, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Eiji HASUNUMA
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Publication number: 20120162947Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Applicant: ANALOG DEVICES, INC.Inventors: Alan O'DONNELL, Santiago IRIARTE, Mark J. MURPHY, Colin LYDEN, Gary CASEY, Eoin Edward ENGLISH
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Publication number: 20120161282Abstract: Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.Type: ApplicationFiled: February 28, 2012Publication date: June 28, 2012Inventors: Vishwanath Bhat, Dan Gealy, Vassil Antonov
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Publication number: 20120161217Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip which includes a semiconductor integrated circuit provided in an insulator, a first pad a pad having an upper surface of which is exposed via an opening formed in the insulator, and capacitors provided in a capacitor region of the semiconductor chip under the pad. The capacitors are provided in the capacitor region to satisfy a rule of a coverage. And contacts respectively connected to two electrodes of the capacitors are provided at positions that do not vertically overlap the opening.Type: ApplicationFiled: September 18, 2011Publication date: June 28, 2012Inventor: Jumpei SATO
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Publication number: 20120161215Abstract: A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Inventor: Nick Lindert