Metal-insulator-semiconductor (e.g., Mos Capacitor) (epo) Patents (Class 257/E29.345)
-
Patent number: 8698280Abstract: In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.Type: GrantFiled: December 8, 2011Date of Patent: April 15, 2014Assignee: Spansion LLCInventor: Koji Shimbayashi
-
Publication number: 20140091845Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Han Wui THEN, Sansaptak DASGUPTA, Gerhard SCHROM, Valluri R. RAO, Robert S. CHAU
-
Patent number: 8686496Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.Type: GrantFiled: November 30, 2011Date of Patent: April 1, 2014Inventor: Noriaki Mikasa
-
Patent number: 8669605Abstract: A semiconductor device comprises a circuit cell and a basic end cell. The circuit cell includes a plurality of elements aligned in a first direction, and the basic end cell is arranged adjacent to the circuit cell in the first direction and has a compensation capacitor capable of being connected to a supply voltage of the circuit cell. In the semiconductor device, a diffusion layer forming the compensation capacitor extends along the first direction in a predetermined region of the circuit cell.Type: GrantFiled: March 11, 2010Date of Patent: March 11, 2014Inventor: Yoshiaki Shimizu
-
Patent number: 8642422Abstract: In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate, layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.Type: GrantFiled: December 8, 2011Date of Patent: February 4, 2014Assignee: Spansion LLCInventor: Koji Shimbayashi
-
Patent number: 8637958Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.Type: GrantFiled: September 14, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Abhishek Dube, Subramanian S. Iyer, Babar Ali Khan, Oh-jung Kwon, Junedong Lee, Paul C. Parries, Chengwen Pei, Gerd Pfeiffer, Ravi Todi, Geng Wang
-
Patent number: 8633533Abstract: A capacitor and a method of manufacturing the same are provided. A dummy capacitor group is formed in the peripheral circuit area and includes a dummy storage node contact unit, a dielectric, and a dummy plate electrode. A metal oxide semiconductor (MOS) capacitor is formed in the peripheral circuit area and connected to the dummy capacitor group in parallel. Capacitance of the dummy capacitor group may be greater than that of the MOS capacitor.Type: GrantFiled: December 30, 2011Date of Patent: January 21, 2014Assignee: SK Hynix Inc.Inventor: Jong Su Kim
-
Patent number: 8633535Abstract: According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.Type: GrantFiled: June 9, 2011Date of Patent: January 21, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kouji Matsuo, Toshiyuki Enda, Nobutoshi Aoki, Toshihiko Iinuma
-
Patent number: 8629506Abstract: A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.Type: GrantFiled: March 19, 2009Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Haining S. Yang
-
Patent number: 8614472Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.Type: GrantFiled: August 19, 2011Date of Patent: December 24, 2013Assignee: Integrated Device Technology, Inc.Inventors: Syed S. Islam, Mansour Keramat
-
Patent number: 8604587Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.Type: GrantFiled: January 19, 2010Date of Patent: December 10, 2013Assignee: Texas Instruments IncorporatedInventors: Edmund Burke, Satyavolu Srinivas Papa Rao, Timothy Alan Rost
-
Publication number: 20130320421Abstract: A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.Type: ApplicationFiled: May 29, 2012Publication date: December 5, 2013Inventors: Kai-Ling Chiu, Chao-Sheng Cheng, Chih-Yu Tseng, Yu-Jen Liu
-
Patent number: 8592897Abstract: A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.Type: GrantFiled: December 21, 2012Date of Patent: November 26, 2013Assignee: Micron Technology, Inc.Inventor: Venkatesan Anathan
-
Patent number: 8541868Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.Type: GrantFiled: October 31, 2012Date of Patent: September 24, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
-
Patent number: 8541770Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.Type: GrantFiled: August 16, 2011Date of Patent: September 24, 2013Assignee: Micron Technology, Inc.Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
-
Patent number: 8535999Abstract: Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.Type: GrantFiled: October 12, 2010Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Lahir Adam, Bruce B. Doris, Sanjay Mehta, Zhengmao Zhu
-
Patent number: 8536633Abstract: The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic-discharge (ESD) protection and a voltage-stabilizing capacitor, and a method for manufacturing the same and is applied to a chip, including a P-type substrate, a conductor layer, a first N-type doping region, a second N-type doping region, and an N-type well. The conductor layer is coupled to the ground; the first N-type doping region is coupled to the power supply; the second N-type doping region is coupled to a VDD pad (power-supply pad). Thereby, when the chip is not installed or not operating, the MOSFET can be used for ESD protection. When the chip is operating, the conductor layer, the first N-type doping region, the second N-type doing region, and the N-type well form a gate capacitor as a voltage-stabilizing capacitor between the power supply and the ground. Hence, the objective of fully utilization is achieved. In addition, the chip size is saved and thus the cost thereof is reduced.Type: GrantFiled: January 3, 2008Date of Patent: September 17, 2013Assignee: Realtek Semiconductor Corp.Inventor: Yi-Lin Chen
-
Publication number: 20130222045Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Applicant: TRANSPHORM INC.Inventor: Yifeng Wu
-
Publication number: 20130193499Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chung-Hui CHEN
-
Publication number: 20130181269Abstract: A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type. A contact structure is in direct contact with the first and second implant regions and the electrode. A third implant region has a second dopant type different from the first dopant type. A bulk contact is provided on the third implant.Type: ApplicationFiled: January 13, 2012Publication date: July 18, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Chung-Hui CHEN
-
Publication number: 20130175590Abstract: A semiconductor device includes: an element isolation region formed in a substrate that defines an active region, a conductive layer formed on the active region, a first insulating film formed between the active region and the conductive layer and having a first thickness, and a second insulating film formed between the active region and the conductive layer and spans at least part of a boundary between the active region and the element isolation region and having a second thickness which is greater than the first thickness.Type: ApplicationFiled: September 13, 2012Publication date: July 11, 2013Inventor: Myoung-Soo Kim
-
Publication number: 20130161711Abstract: A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.Type: ApplicationFiled: September 13, 2012Publication date: June 27, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Soo NAM, Joon-Suk Oh, Hye-Young Park
-
Patent number: 8471362Abstract: A three-dimensional (3D) semiconductor device including a plurality of stacked layers and a through-silicon via (TSV) electrically connecting the plurality of layers, in which in signal transmission among the plurality of layers, the TSV transmits a signal that swings in a range from an offset voltage that is higher than a ground voltage to a power voltage, thereby minimizing an influence of a metal-oxide-semiconductor (MOS) capacitance of TSV.Type: GrantFiled: April 5, 2011Date of Patent: June 25, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Jong-joo Lee
-
Patent number: 8472251Abstract: A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (greater than 80%) between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.Type: GrantFiled: February 10, 2009Date of Patent: June 25, 2013Assignee: Aplus Flash Technology, Inc.Inventors: Peter Wung Lee, Fu-Chang Hsu
-
Patent number: 8471363Abstract: A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.Type: GrantFiled: September 27, 2011Date of Patent: June 25, 2013Assignee: Denso CorporationInventors: Kazushi Asami, Yasuhiro Kitamura
-
Publication number: 20130146958Abstract: A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.Type: ApplicationFiled: April 13, 2012Publication date: June 13, 2013Inventors: You-Song Kim, Jin-Ki Jung
-
Publication number: 20130126953Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen
-
Publication number: 20130126955Abstract: Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang
-
Publication number: 20130119449Abstract: A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.Type: ApplicationFiled: November 15, 2011Publication date: May 16, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Ji CHEN, Wei Yu MA, Ta-Pen GUO, Hsien-Wei CHEN, Hao-Yi TSAI
-
Publication number: 20130107630Abstract: Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Applicant: INVENSAS CORPORATIONInventors: David Edward Fisch, Michael Curtis Parris
-
Patent number: 8431982Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.Type: GrantFiled: January 19, 2011Date of Patent: April 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Myoungsoo Kim, Yoonkyung Choi, Eun Young Lee, Sungil Jo
-
Patent number: 8426867Abstract: A plurality of thin film capacitor parts are provided in respective regions each surrounded by a plurality of gate metal lines (12) and a plurality of data signal lines (11) intersecting perpendicularly to each other on a glass substrate (1), and each of the thin film capacitor parts has a lower electrode (3), a gate insulating film, and an upper electrode (5), which are provided in this order. Adjacent upper electrodes (5) are electrically connected to each other via a corresponding first wire (8), which is positioned above the adjacent upper electrodes (5) and intersects with one of the data signal lines (11). This makes it possible to provide a thin film capacitor, which includes the lower electrodes (3) each having the same thickness in a center portion and an edge portion, and the upper electrodes (5) that are connected to each other by using a corresponding connecting wire with low possibility of disconnection.Type: GrantFiled: July 2, 2008Date of Patent: April 23, 2013Assignee: Sharp Kabushiki KaishaInventor: Hiroyuki Moriwaki
-
Publication number: 20130092993Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.Type: ApplicationFiled: October 16, 2012Publication date: April 18, 2013Applicant: Renesas Electronics CorporationInventor: Renesas Electronics Corporation
-
Patent number: 8410578Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated passive device. In accordance with embodiments, the monolithically integrated passive device includes an inductor formed from damascene structures.Type: GrantFiled: December 7, 2010Date of Patent: April 2, 2013Assignee: Semiconductor Components Industries, LLCInventors: Sallie Hose, Peter A. Burke, Li Jiang, Sudhama C. Shastri
-
Patent number: 8410534Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.Type: GrantFiled: February 8, 2012Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventor: Steven H. Voldman
-
Publication number: 20130075801Abstract: A method for producing a capacitive structure in a semiconductor body includes forming a first trench in a first surface of the semiconductor body, forming a first dielectric layer on sidewalls and the bottom of the first trench, forming a first electrode layer on the first dielectric layer, forming at least one second trench by removing at least one part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap, forming a second dielectric layer on sidewalls and the bottom of the at least one second trench, and forming a second electrode layer on the second dielectric layer.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: Infineon Technologies Austria AGInventors: Hans Weber, Roman Knoefler, Kurt Sorschag
-
Publication number: 20130076335Abstract: An integrated circuit includes at least one FLASH memory array and at least one capacitor array disposed over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures each includes a first capacitor electrode disposed over the substrate. A second capacitor electrode is disposed over the first capacitor electrode. A third capacitor electrode is disposed adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is disposed adjacent to second sidewalls of the first and second capacitor electrodes.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yvonne LIN, Wen-Ting CHU
-
Publication number: 20130056763Abstract: An object is to provide a semiconductor device that can realize a function of a thyristor without complication of the process. A semiconductor device including a memory circuit that stores a predetermined potential by reset operation and initialization operation is provided with a circuit that rewrite data in the memory circuit in accordance with supply of a trigger signal. The semiconductor device has a structure in which a current flowing through the semiconductor device is supplied to a load by rewriting data in the memory circuit, and thus can function as a thyristor.Type: ApplicationFiled: November 5, 2012Publication date: March 7, 2013Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Semiconductor Energy Laboratory Co., Ltd.
-
Publication number: 20130056813Abstract: A capacitor structure applied to an integrated circuit (IC) is provided. The capacitor structure includes a metal-oxide semiconductor (MOS) capacitor and two metal structures with different structures. The MOS capacitor has a first terminal and a second terminal. The two metal capacitors are formed above the MOS capacitor and respectively coupled between the first terminal and the second terminal. Subject to the confined chip area, the capacitance of the above-mentioned capacitor structure can still reach the design value, and the above-mentioned capacitor structure is further characterized by a large amount of current flow.Type: ApplicationFiled: October 14, 2011Publication date: March 7, 2013Applicant: PHISON ELECTRONICS CORP.Inventor: Tien-Lung Chen
-
Patent number: 8384155Abstract: A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned salicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.Type: GrantFiled: April 5, 2007Date of Patent: February 26, 2013Assignee: eMemory Technology Inc.Inventors: Chrong-Jung Lin, Hsin-Ming Chen, Ya-Chin King
-
Publication number: 20130043562Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.Type: ApplicationFiled: October 25, 2012Publication date: February 21, 2013Applicant: INFINEON TECHNOLOGIES AGInventor: INFINEON TECHNOLOGIES AG
-
Patent number: 8378453Abstract: Embodiments of the present disclosure include devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like.Type: GrantFiled: April 29, 2011Date of Patent: February 19, 2013Assignee: Georgia Tech Research CorporationInventors: Andrei G. Fedorov, Craig Green, Yogendra Joshi
-
Patent number: 8373216Abstract: Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.Type: GrantFiled: October 27, 2010Date of Patent: February 12, 2013Assignee: Renesas Electronics CorporationInventors: Hiraku Chakihara, Yasushi Ishii
-
Patent number: 8367506Abstract: A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor.Type: GrantFiled: June 4, 2007Date of Patent: February 5, 2013Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
-
Patent number: 8368139Abstract: A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.Type: GrantFiled: December 6, 2011Date of Patent: February 5, 2013Assignee: Micron Technology, Inc.Inventor: Venkatesan Ananthan
-
Publication number: 20130026551Abstract: A semiconductor integrated circuit including a large capacity reservoir capacitor to provide suitable power is provided. The semiconductor integrated circuit includes a semiconductor substrate in which a cell area and a peripheral circuit area are defined, a MOS capacitor formed on the semiconductor substrate corresponding to the peripheral circuit area, and a dummy capacitor group formed on the peripheral circuit area to overlap the MOS capacitor. One electrode of the MOS capacitor and one electrode of the dummy capacitor group are connected to each other and the other electrode of the MOS capacitor and the other electrode of the dummy capacitor group are connected to difference voltage sources from each other.Type: ApplicationFiled: September 14, 2012Publication date: January 31, 2013Applicant: SK HYNIX INC.Inventor: Jong Su Kim
-
Publication number: 20130026549Abstract: A capacitor and a method of manufacturing the same are provided. A dummy capacitor group is formed in the peripheral circuit area and includes a dummy storage node contact unit, a dielectric, and a dummy plate electrode. A metal oxide semiconductor (MOS) capacitor is formed in the peripheral circuit area and connected to the dummy capacitor group in parallel. Capacitance of the dummy capacitor group may be greater than that of the MOS capacitor.Type: ApplicationFiled: December 30, 2011Publication date: January 31, 2013Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jong Su KIM
-
Publication number: 20130015514Abstract: A non-volatile memory cell that includes a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor configured in parallel with the gate of the sense transistor. The coupling capacitor, sense transistor and tunnelling capacitor share a common floating gate electrode and the sense transistor includes source and drain regions arranged such that the tunnelling capacitor is defined by an overlap between the floating gate electrode and the drain region of the sense transistor. Word-line contacts may be to a separate active area from the coupling capacitor. This and/or other features can help to reduce Frenkel-Poole conduction.Type: ApplicationFiled: April 18, 2012Publication date: January 17, 2013Applicant: CAMBRIDGE SILICON RADIO LIMITEDInventor: Rainer Herberholz
-
Patent number: 8350307Abstract: Provided is a semiconductor memory device including a capacitor structure extending over core and peripheral areas of a substrate. Respective portions of the capacitor structure function as memory cell capacitors in the core area and as first and second capacitors in the peripheral area. A combination of the first and second capacitors functions as a first power decoupling capacitor, and a transistor disposed in the peripheral area functions as a second power decoupling capacitor.Type: GrantFiled: August 12, 2009Date of Patent: January 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Sunghoon Kim
-
Publication number: 20120306567Abstract: A capacitance structure comprises a plurality of metal oxide silicon (MOS) capacitors. A first end of each MOS capacitor of the plurality of MOS capacitors is coupled together at an effective node. A second end of each MOS capacitor of the plurality of MOS capacitors is configured to receive a respective different signal. Each first end of each MOS capacitor of the plurality of MOS capacitors thereby functions as an input end of a capacitor with a capacitance value determined based on the respective different signal. An effective capacitance value thereby results at the effective node.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Hyun-Sung HONG