Position-sensitive And Lateral-effect Photodetector (e.g., Quadrant Photodiode) (epo) Patents (Class 257/E31.115)
  • Patent number: 11841217
    Abstract: A multi-function sensor system including an auto-alignment system. The multi-function sensor system includes a laser module configured to provide a transmit beam and an auto-alignment beam, a shared aperture component, a first channel configured to direct the transmit beam and the auto-alignment beam to the shared aperture component, a second channel configured to receive the transmit beam from the shared aperture component and provide a receive beam to the shared aperture component, and a third channel including a passive imager configured to receive the auto-alignment beam and a first portion of the receive beam from the shared aperture component, wherein the auto-alignment beam propagates through the passive imager to provide an indication of a line of sight (LOS) of the transmit beam relative to a field of view (FOV) of the passive imager.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 12, 2023
    Assignee: RAYTHEON COMPANY
    Inventor: Lacy G. Cook
  • Patent number: 11837473
    Abstract: Methods for adjusting a work function of a structure in a substrate leverage near surface doping. In some embodiments, a method for adjusting a work function of a structure in a substrate may include growing an epitaxial layer on surfaces of the structure to form a homogeneous passivation region as part of a substrate material of the substrate and performing a dopant diffusion process to further embed the dopants into surfaces of the structure to adjust a work function of the structure, wherein the dopant diffusion process is performed at less than approximately 450 degrees Celsius.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: December 5, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Taichou Papo Chen
  • Patent number: 11558569
    Abstract: Apparatus for optical sensing includes first matrix of optical sensing elements, arranged on a semiconductor substrate in rows and columns. A second matrix of storage nodes is arranged on the substrate such that respective first and second storage nodes in the second matrix are disposed in proximity to each of the sensing elements within the first matrix. Switching circuitry couples each of the sensing elements to transfer photocharge to the respective first and second storage nodes. Control circuitry controls the switching circuitry in a depth sensing mode such that over a series of detection cycles, each of the sensing elements and a first neighboring sensing element are connected together to the respective first storage node during the first detection interval, and each of the sensing elements and the second neighboring sensing element are connected together to the respective second storage node during the second detection interval.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 17, 2023
    Assignee: APPLE INC.
    Inventors: Gennadiy Agranov, Thierry Oggier
  • Patent number: 11381426
    Abstract: Systems and methods are provided for enabling lower-bandwidth hardware components to support higher data rates. In particular, aspects of the disclosed systems and methods use Raised Cosine pulse shaping in short-reach links to band limit the signal spectra and thereby enable existing, such lower-bandwidth components to support higher data rates.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: July 5, 2022
    Assignee: Georgia Tech Research Corporation
    Inventors: Siddharth Jacob Varughese, Joseph Justin Lavrencik, Stephen E. Ralph, Varghese Antony Thomas
  • Patent number: 9697605
    Abstract: A method for the three-dimensional imaging of a sample in which image information from different depth planes of the sample is stored in a spatially resolved manner, and the three-dimensional image of the sample is subsequently reconstructed from this stored image information is provided. A reference structure is applied to the illumination light, at least one fluorescing reference object is positioned next to or in the sample, images of the reference structure of the illumination light, of the reference object are recorded from at least one detection direction and evaluated. The light sheet is brought into an optimal position based on the results and image information of the reference object and of the sample from a plurality of detection directions is stored. Transformation operators are obtained on the basis of the stored image information and the reconstruction of the three-dimensional image of the is based on these transformation operators.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: July 4, 2017
    Assignee: CARL ZEISS MICROSCOPY GMBH
    Inventors: Helmut Lippert, Benno Radt, Michael Kempe, Christian Dietrich
  • Patent number: 9545220
    Abstract: The invention is a system and method for measuring 3D distances and dimensions of objects in endoscopic images by using a light plane to make Euclidean and geodesic measurements. The endoscopic measurement system of the invention comprises a flexible or rigid endoscopic device equipped with standard visualization means and a module containing components for generating a light plane. Based on triangulation, the intersection curve between the light lane and the object of interest is measurable in 3D in the coordinate system of the visualization means.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: January 17, 2017
    Assignee: V.T.M (Virtual Tape Measure) Technologies Ltd.
    Inventor: Avishay Sidlesky
  • Patent number: 9473766
    Abstract: A method and apparatus for three dimensional viewing of images is presented. Left eye viewing point (LEVP) imagery is passed through a left eye filter to obtain a filtered LEVP imagery. Right eye viewing point (REVP) imagery is passed through a right eye filter to obtain a filtered REVP imagery. The filtered LEVP imagery is projected on a display and the filtered REVP imagery is projected on the display. A user wearing polarized glasses is able to view the filtered LEVP imagery and the filtered REVP imagery as three-dimensional imagery on the display. The three dimensional imagery can be augmented.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: October 18, 2016
    Inventors: David Byron Douglas, Robert E. Douglas
  • Patent number: 9013023
    Abstract: A photoelectric element includes a first electrode; and a second electrode positioned so as to face the first electrode; and a semiconductor disposed on a face of the first electrode, the face being positioned so as to face the second electrode; and a photosensitizer carried on the semiconductor; and a first charge-transport layer interposed between the first electrode and the second electrode; and a second charge-transport layer interposed between the first charge-transport layer and the second electrode. The first charge-transport layer and the second charge-transport layer contain different oxidation-reduction materials. The oxidation-reduction material in the first charge-transport layer has an oxidation-reduction potential higher than an oxidation-reduction potential of the oxidation-reduction material in the second charge-transport layer.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 21, 2015
    Assignees: Panasonic Corporation, Waseda University
    Inventors: Michio Suzuka, Takashi Sekiguchi, Naoki Hayashi, Hiroyuki Nishide, Kenichi Oyaizu, Fumiaki Kato
  • Patent number: 8981517
    Abstract: A solid-state image pickup element 1 is structured so as to include: a semiconductor layer 2 having a photodiode formed therein, photoelectric conversion being carried out in the photodiode; a first film 21 having negative fixed charges and formed on the semiconductor layer 2 in a region in which at least the photodiode is formed; and a second film 22 having the negative fixed charges, made of a material different from that of the first film 21 having the negative fixed charges, and formed on the first film 21 having the negative fixed charges.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Itaru Oshiyama, Susumu Hiyama
  • Patent number: 8896037
    Abstract: A solid-state imaging device including: a semiconductor layer; a charge accumulation region configured to be formed inside the semiconductor layer and serve as part of a photodiode; and a reflective surface configured to be disposed inside or under the charge accumulation region and be so formed as to reflect light that has passed through the charge accumulation region and direct the light toward a center part of the charge accumulation region.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventors: Harumi Ikeda, Masashi Nakazawa
  • Patent number: 8809877
    Abstract: A semiconductor voltage transformation structure is provided. The semiconductor voltage transformation structure includes: a first electrode layer ; an electricity-to-light conversion layer formed on the first electrode layer; a second electrode layer formed on the electricity-to-light conversion layer; a first isolation layer formed on the second electrode layer; a third electrode layer formed on the first isolation layer; a light-to-electricity conversion layer formed on the third electrode layer; and a fourth electrode layer formed on the light-to-electricity conversion layer, in which the first isolation layer, the second electrode layer and the third electrode layer are transparent to a working light emitted by the electricity-to-light conversion layer.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: August 19, 2014
    Inventor: Lei Guo
  • Patent number: 8785994
    Abstract: An X-ray detector including: a substrate that is divided into a light detection area and a non-detection area and includes a plurality of pixels; a photodiode disposed on the light detection area; a thin film transistor that is disposed on the non-detection area and is electrically connected to a lower portion of the photodiode; a plurality of wires that are electrically connected to the thin film transistor and are positioned on the non-detection area; at least one insulating layer disposed so as to cover at least the thin film transistor and the plurality of wires; a scintillator layer disposed on the at least one insulating layer over an entire surface of the substrate; and a shielding part disposed between the at least one insulating layer and the scintillator layer to shield the non-detection area.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: July 22, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dong-Hyuk Kim
  • Patent number: 8716722
    Abstract: A photosensor chip package structure comprises a substrate, a light-emitting chip and a photosensor chip including an ambient light sensing unit and a proximity sensing unit. The substrate has a first basin, a second basin and a light-guiding channel. The openings of the first and second basins respectively face different directions. One opening of the light-guiding channel and the opening of the first basin face the same direction. The other opening of the light-guiding channel interconnects with the second basin. The light-emitting chip is arranged in the first basin. The photosensor chip is arranged in the second basin. The light-guiding channel conducts the light generated by the light-emitting chip and the ambient light to the photosensor chip. The photosensor chip operates as soon as it receives the light generated by the light-emitting chip and/or the ambient light.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: May 6, 2014
    Assignee: TXC Corporation
    Inventor: Yin-Ming Peng
  • Patent number: 8669135
    Abstract: A system and method for fabricating a 3D image sensor structure is disclosed. The method comprises providing an image sensor with a backside illuminated photosensitive region on a substrate, applying a first dielectric layer to the first side of the substrate opposite the substrate side where image data is gathered, and applying a semiconductor layer that is optionally polysilicon, to the first dielectric layer. A least one control transistor may be created on the first dielectric layer, within the semiconductor layer and may optionally be a row select, reset or source follower transistor. An intermetal dielectric may be applied over the first dielectric layer; and may have at least one metal interconnect disposed therein. A second interlevel dielectric layer may be disposed on the control transistors. The dielectric layers and semiconductor layer may be applied by bonding a wafer to the substrate or via deposition.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang
  • Patent number: 8664739
    Abstract: In accordance with the invention, an improved image sensor includes an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 4, 2014
    Assignee: Infrared Newco, Inc.
    Inventors: Clifford A. King, Conor S. Rafferty
  • Patent number: 8629423
    Abstract: In the present invention, one or more inventive designs and techniques allow formation of high speed complementary metal oxide semiconductor (CMOS) process compatible tunneling devices that are formed on low dielectric loss sheet-substrates (such as silicon or germanium for infrared or quartz and sapphire for visible or near infrared) having the first and the second smooth planar surfaces and an intermediate surface in the form of a hole, or slit, or a side edge, which extends between and connects the first and second surfaces, so that deposited from opposite sides of the sheet-substrate the first metal layer followed by its oxidation or nanometer thickness tunneling dielectric coating and the second metal layer have an overlapped coupled area within the intermediate surface, thus forming a non-planar metal-insulator-metal (MIM) tunneling junction of low capacitance and high cut-off frequency, which is capable to operate at room temperature at terahertz, infrared, and even optical frequencies.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: January 14, 2014
    Inventor: Nikolai Kislov
  • Patent number: 8368122
    Abstract: A multiple-junction photoelectric device includes a substrate with a first conducting layer thereon, at least two elementary photoelectric devices of p-i-n or p-n configuration, with a second conducting layer thereon, and at least one intermediate layer between two adjacent elementary photoelectric devices. The intermediate layer has, on the incoming light side, opposite top and bottom faces, the top and bottom faces having respectively a surface morphology including inclined elementary surfaces so ?90bottom is smaller than ?90top by at least 3°, preferably 6°, more preferably 10°, and even more preferably 15°; where ?90top is the angle for which 90% of the elementary surfaces of the top face of the intermediate layer have an inclination equal to or less than this angle, and ?90bottom is the angle for which 90% of the elementary surfaces of the bottom face of the intermediate layer have an inclination equal to or less than this angle.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: February 5, 2013
    Assignee: Universite de Neuchatel
    Inventors: Didier Domine, Peter Cuony, Julien Bailat
  • Patent number: 8299484
    Abstract: An optoelectronic semiconductor chip including a radiation passage area, where a contact metallization is applied to the radiation passage area, and a first reflective layer sequence is applied to that surface of the contact metallization which is remote from the radiation passage area, and an optoelectronic component that includes such a chip.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: October 30, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Stefan Grötsch, Norbert Linder
  • Patent number: 8288808
    Abstract: The present disclosure uses at least two cascaded photodetectors. Device area is increased to provide a bigger current than a single photodetector under the same bandwidth. Hence, bandwidth efficiency (BRP) and saturation current-bandwidth product (SCBP) are improved for a high speed, a high responsivity and a high bandwidth with simple structure and low cost.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: October 16, 2012
    Assignee: National Central University
    Inventors: Jin-Wei Shi, Feng-Ming Kuo
  • Patent number: 8263966
    Abstract: A photodetector 1 according to an embodiment of the present invention includes: an n-type InAs substrate 12; an n-type InAs buffer layer 14 formed on the n-type InAs substrate 12; an n-type InAs light absorbing layer 16 formed on the n-type InAs buffer layer 14; an InAsXPYSb1-X-Y cap layer 18 (X?0, Y>0) formed on the n-type InAs light absorbing layer 16; a first inorganic insulating film 20 formed on the cap layer 18, and having an opening portion 20h in a deposition direction; a p-type impurity semiconductor region 24 fowled by diffusing a p-type impurity from the opening portion 20h of the first inorganic insulating film 20, and reaching from the cap layer 18 to an upper layer of the n-type InAs light absorbing layer 16; and a second inorganic insulating film 22 formed on the first inorganic insulating film 20 and on the p-type impurity semiconductor region 24.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 11, 2012
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Akihito Yokoi
  • Patent number: 8258559
    Abstract: The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a surface of the photodiode are discharged to the power voltage terminal through the channel.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: September 4, 2012
    Assignee: Siliconfile Technologies Inc.
    Inventor: Byoung-Su Lee
  • Patent number: 8212327
    Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: July 3, 2012
    Assignee: SiOnyx, Inc.
    Inventors: Neal T. Kurfiss, James E. Carey, Xia Li
  • Patent number: 8203194
    Abstract: Disclosed are an image sensor and a method of manufacturing the same. A metal wiring consisting of a lower metal wiring, an upper metal wiring, and a plug connecting the lower and upper metal wirings, in which the lower and upper metal wiring are made of a transparent conductive film pattern, is formed on a substrate with devices formed thereon, the devices including a photodiode and gate electrodes. Then, a passivation film, a color filter, and a microlens are sequentially formed on the metal wiring. All or a portion of the metal wiring is formed in a transparent conductive film pattern. As such, the metal wiring is formed on the photodiode.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: June 19, 2012
    Assignee: Intellectual Ventures II LLC
    Inventor: Hee Jeen Kim
  • Publication number: 20120043584
    Abstract: A quad photoreceiver includes a low capacitance quad InGaAs p-i-n photodiode structure formed on an InP (100) substrate. The photodiode includes a substrate providing a buffer layer having a metal contact on its bottom portion serving as a common cathode for receiving a bias voltage, and successive layers deposited on its top portion, the first layer being drift layer, the second being an absorption layer, the third being a cap layer divided into four quarter pie shaped sections spaced apart, with metal contacts being deposited on outermost top portions of each section to provide output terminals, the top portions being active regions for detecting light. Four transimpedance amplifiers have input terminals electrically connected to individual output terminals of each p-i-n photodiode.
    Type: Application
    Filed: August 23, 2010
    Publication date: February 23, 2012
    Inventors: Abhay M. Joshi, Shubhashish Datta
  • Patent number: 8101940
    Abstract: A photodetector 1 according to an embodiment of the present invention includes: an n-type InAs substrate 12; an n-type InAs buffer layer 14 formed on the n-type InAs substrate 12; an n-type InAs light absorbing layer 16 formed on the n-type InAs buffer layer 14; an InAsXPYSb1-X-Y cap layer 18 (X?0, Y>0) formed on the n-type InAs light absorbing layer 16; a first inorganic insulating film 20 formed on the cap layer 18, and having an opening portion 20h in a deposition direction; a p-type impurity semiconductor region 24 formed by diffusing a p-type impurity from the opening portion 20h of the first inorganic insulating film 20, and reaching from the cap layer 18 to an upper layer of the n-type InAs light absorbing layer 16; and a second inorganic insulating film 22 formed on the first inorganic insulating film 20 and on the p-type impurity semiconductor region 24.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: January 24, 2012
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Akihito Yokoi
  • Patent number: 8026538
    Abstract: A photo-detecting apparatus includes a photodiode that coverts light into electricity, a reverse-voltage switching unit that switches a reverse voltage to be applied to the photodiode, a current-difference detecting unit that detects a change in an output current of the photodiode occurring due to switching of the reverse voltage as a current difference, a correspondence retaining unit that retains a correspondence between the current difference and a dark current, a dark-current calculating unit that calculates a dark current by referring to the correspondence based on the current difference detected by the current-difference detecting unit, and a dark-current correcting unit that corrects the output current of the photodiode based on the dark current to find a photocurrent obtained through photoelectric conversion.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 27, 2011
    Assignee: Fujitsu Limited
    Inventors: Tomoaki Takeyama, Keiko Sasaki, Shinichirou Muro
  • Patent number: 8018015
    Abstract: A pixel cell having a photo-conversion device at a surface of a substrate and at least one contact area from which charge or a signal is output or received. A first insulating layer is located over the photo-conversion device and the at least one contact area. The pixel cell further includes at least one conductor in contact with the at least one contact area. The conductor includes a polysilicon material extending through the first insulating layer and in contact with the at least one contact area. Further, a conductive material, which includes at least one of a silicide and a refractory metal, can be over and in contact with the polysilicon material.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 13, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 7972934
    Abstract: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: July 5, 2011
    Assignee: Icemos Technology Ltd.
    Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
  • Patent number: 7973377
    Abstract: In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: July 5, 2011
    Assignee: Infrared Newco, Inc.
    Inventors: Clifford A. King, Conor S. Rafferty
  • Patent number: 7964925
    Abstract: Various embodiments of the present invention are directed to a photodiode module including a structure configured to selectively couple light to a dielectric-surface mode of a photonic crystal of the photodiode module. In one embodiment of the present invention, a photodiode module includes a semiconductor structure having a p-region and an n-region. The photodiode module further includes a photonic crystal having a surface positioned adjacent to the semiconductor structure. A diffraction grating of the photodiode module may be positioned and configured to selectively couple light incident on the diffraction grating to a dielectric-surface mode associated with the surface of the photonic crystal. In another embodiment of the present invention, a photodiode apparatus includes multiple, stacked photodiode modules, each of which is configured to selectively absorb light at a selected wavelength or range of wavelengths.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: June 21, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David Fattal, Jason Blackstock, Duncan Stewart
  • Patent number: 7943957
    Abstract: A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor region 60 includes a high concentration of n-type impurity. The intermediate semiconductor region 53 includes a low concentration of n-type impurity. The surface semiconductor region 54 includes p-type impurity.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: May 17, 2011
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masato Taki, Masahiro Kawakami, Kiyoharu Hayakawa, Masayasu Ishiko
  • Patent number: 7910479
    Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: March 22, 2011
    Assignee: Icemos Technology Ltd.
    Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
  • Patent number: 7880207
    Abstract: A photo detector device comprising a first layer comprising a first material, and a second layer arranged adjacent to the first layer, the second layer comprising strained silicon, wherein the second layer further comprises a light absorption region located substantially within the strained silicon, wherein the first or the second layer is arranged on a substrate.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthias Fertig, Thomas E. Morf, Jonas R. Weiss, Thomas Pflueger, Nikolaj Moll
  • Patent number: 7816755
    Abstract: A pixel space is narrowed without increasing PN junction capacitance. A photoelectric conversion device includes a plurality of pixels arranged therein, each including a first impurity region of a first conductivity type forming a photoelectric conversion region, a second impurity region of a second conductivity type forming a signal acquisition region arranged in the first impurity region, a third impurity region of the first conductivity type and a fourth impurity region of the first conductivity type are arranged in a periphery of each pixel for isolating the each pixel, the fourth impurity region is disposed between adjacent pixels, and an impurity concentration of the fourth impurity region is smaller than an impurity concentration of the third impurity region.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: October 19, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuo Yamazaki, Tetsunobu Kochi
  • Patent number: 7723206
    Abstract: A photodiode in which increased sensitivity and speed are balanced. The photodiode includes: a semiconductor substrate; a plurality of active regions formed on the substrate by selective epitaxial growth; and a comb electrode provided for each of the plurality of active regions and in communication with each other to electrically connect the active regions together.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: May 25, 2010
    Assignees: FUJIFILM Corporation, Massachusetts Institute of Technology
    Inventors: Yukiya Miyachi, Wojciech P. Giziewicz, Jurgen Michel, Lionel C. Kimerling
  • Patent number: 7714369
    Abstract: A semiconductor chip that has a photodiode formed on it, a semiconductor device including the semiconductor chip, and manufacturing methods thereof. A second semiconductor region 11 is formed in light-receiving region R of first semiconductor region 10. First bumps 12 are formed outside light-receiving region R. Second bump 13 is formed in a ring-shape around light-receiving region R between region R and first bumps 12. Semiconductor chip T is assembled on assembly substrate S, and resin layer 30 is formed between chip T and substrate S in the region outside of said light-receiving region R.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: May 11, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Yoichi Okumura, Ryoichi Kojima
  • Patent number: 7687875
    Abstract: An image sensor includes a semiconductor layer, and first and second photoelectric converting units including first and second impurity regions in the semiconductor layer that are spaced apart from each other and that are at about an equal depth in the semiconductor layer, each of the impurity regions including an upper region and a lower region. A width of the lower region of the first impurity region may be larger than a width of the lower region of the second impurity region, and widths of upper regions of the first and second impurity regions are equal.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: March 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yun-ki Lee
  • Publication number: 20100032710
    Abstract: This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits one to fabricate thin 4 inch and 6 inch wafer using the physical support provided by a n+ deep diffused layer and/or p+ deep diffused layer. Consequently, the present invention delivers high device performances, such as low crosstalk, low radiation damage, high speed, low leakage dark current, and high speed, using a thin active layer.
    Type: Application
    Filed: July 8, 2009
    Publication date: February 11, 2010
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 7615492
    Abstract: A solar cell is prepared. The solar cell is photo-sensitized. The solar cell has a semiconductor layer. And carbon nanotubes are deposited on the semiconductor layer with an arrangement. The solar cell is prepared with a reduced amount of fabrication material, a lowered fabrication cost and a prolonged lifetime.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: November 10, 2009
    Assignee: Atomic Energy Council - Institute of Nuclear Energy Research
    Inventors: Tsun-Neng Yang, Shan-Ming Lan, Ying-Ru Chen, Chin-Chen Chiang, Wei-Yang Ma, Chien-Te Ku
  • Patent number: 7586167
    Abstract: A sensor device includes a substrate having first and second regions of first and second conductivity types, respectively. A junction having a band-gap is formed between the first and second regions. A plasmon source generates plasmons having fields. At least a portion of the plasmon source is formed near the junction, and the fields reduce the band-gap to enable a current to flow through the device.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: September 8, 2009
    Assignee: Virgin Islands Microsystems, Inc.
    Inventors: Jonathan Gorrell, Mark Davidson
  • Patent number: 7579273
    Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: August 25, 2009
    Assignee: Icemos Technology Ltd.
    Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
  • Patent number: 7579668
    Abstract: A method for photo-detecting and an apparatus for the same are provided. The apparatus for photo-detecting includes a first P-N diode and a second P-N diode. The first P-N diode, has a first P-N junction which has a first thickness, by which a first electrical signal is generated when irradiated by light, and the second P-N diode has a second P-N junction which has a second thickness, by which a second electrical signal is generated when irradiated by light. The second thickness is larger than the first thickness and an operation of the first electrical signal and the second electrical signal is proceeded for obtaining a third electrical signal.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: August 25, 2009
    Assignee: National Taiwan University
    Inventors: Chee-Wee Liu, Chun-Hung Lai, Meng-kun Chen, Wei-Shuo Ho
  • Patent number: 7575941
    Abstract: A method of manufacturing of a photodiode is provided. The photodiode is formed on a substrate of a first conductive type. First, an isolation structure is formed in the substrate to define a photosensitive area in the substrate. Thereafter, trenches are formed in the substrate. Next, a doped layer of a second conductive type is formed on the substrate. The doped layer covers at least the inner wall of the trenches and a top portion of the substrate. The method of fabricating the photodiode can reduce overall processing time and cost and improve production efficiency.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: August 18, 2009
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Ko-Hsing Chang, Su-Yuan Chang
  • Patent number: 7576369
    Abstract: This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits one to fabricate thin 4 inch and 6 inch wafer using the physical support provided by a n+ deep diffused layer and/or p+ deep diffused layer. Consequently, the present invention delivers high device performances, such as low crosstalk, low radiation damage, high speed, low leakage dark current, and high speed, using a thin active layer.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: August 18, 2009
    Assignee: UDT Sensors, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 7476598
    Abstract: A photodiode and a method of manufacturing the photodiode are provided. The method includes forming a diode junction structure including a light receiving unit and an electrode unit on a semiconductor substrate, forming a buffer oxide layer and an etching blocking layer on the junction structure, forming an interlayer insulating layer and an intermetal insulating layer and an interconnecting structure, exposing the etching blocking layer by etching the intermetal insulating layer and the interlayer insulating layer, removing a portion of the etching blocking layer and the buffer oxide layer of the light-receiving unit by dry etching, and exposing a semiconductor surface of the light-receiving unit by wet etching.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: January 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Sung Son, Sung-Ryoul Bae, Dong-Kyun Nam
  • Patent number: 7453129
    Abstract: In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: November 18, 2008
    Assignee: Noble Peak Vision Corp.
    Inventors: Clifford Alan King, Conor S. Rafferty
  • Patent number: 7256436
    Abstract: In a thin-film field-effect transistor having a MIS structure, the insulator layer is formed of cyanoethylated dihydroxypropyl pullulan. The TFT is prepared by applying a cyanoethylated dihydroxypropyl pullulan solution onto a gate electrode in the form of a metal layer, drying the applied solution to form an insulator layer, and thereafter, forming a semiconductor layer thereon.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: August 14, 2007
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Ikuo Fukui
  • Patent number: 7164164
    Abstract: A display device has display elements provided inside of pixels, each being formed in vicinity of intersections of signal lines and scanning lines aligned in matrix form; and photoelectric conversion elements, wherein each of the photoelectric conversion elements includes first, second and third semiconductor regions disposed adjacently in sequence in parallel to a surface of a substrate; a first electrode connected to the first semiconductor region; and a second electrode connected to the third semiconductor region, the first semiconductor region being formed by injecting a first conductive impurity in first dose amount; the third semiconductor region being formed by injecting a second conductive impurity in second dose amount; and the second semiconductor region being formed by injecting the first conductive impurity in third dose amount less than the first dose amount.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: January 16, 2007
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Takashi Nakamura, Norio Tada, Masahiro Tada
  • Publication number: 20060292730
    Abstract: A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well.
    Type: Application
    Filed: July 19, 2005
    Publication date: December 28, 2006
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jianping Yang, Chunyan Xin, Jieguang Huo, Yanyong Wang
  • Patent number: 7135750
    Abstract: A photodiode array includes a first photodiode and at least a second photodiode. The first photodiode includes a first active area, a first anti-reflective coating area, and a first residual polysilicon ring. The first anti-reflective coating area and the first residual polysilicon ring are formed asymmetrically over the first active area. The second photodiode includes a second active area, a second anti-reflective coating area, and a second residual polysilicon ring. The second anti-reflective coating area and the second residual polysilicon ring are formed asymmetrically over the second active area. The first anti-reflective coating area is formed over a region of the first active region adjacent to the second photodiode, and the second anti-reflective coating area is formed over a region of the second active region adjacent to the first photodiode.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: November 14, 2006
    Assignee: Polar Semiconductor, Inc.
    Inventors: John C. Beckman, Noel P. Hoilien