Shape Of Potential Barrier (epo) Patents (Class 257/E33.007)
  • Patent number: 8993999
    Abstract: According to an embodiment, a semiconductor light emitting device is configured to emit light by energy relaxation of an electron between subbands of a plurality of quantum wells. The device includes an active layer and at least a pair of cladding layers. The active layer is provided in a stripe shape extending in a direction parallel to an emission direction of the light, and includes the plurality of quantum wells; and the active layer emits the light with a wavelength of 10 ?m or more. Each of the cladding layers is provided both on and under the active layer respectively and have a lower refractive index than the active layer. At least one portion of the cladding layers contains a material having a different lattice constant from the active layer and has a lower optical absorption at a wavelength of the light than the other portion.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeyuki Takagi, Hidehiko Yabuhara
  • Patent number: 8921887
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumi Masunaga, Ryota Kitagawa, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Patent number: 8779456
    Abstract: An LED device having plasmonically enhanced emission is provided. The device includes an inverted LED structure with a coating of metal nanoparticles on the surface chosen to match the plasmonic response to the peak emission from the active quantum well (QW) emission region of the LED. The active QW emission region is separated from the metal nanoparticles on the surface by a thin n-type contact layer disposed on a top side of the active QW emission. A p-type layer is disposed immediately beneath the active QW emission region and injects holes into the active QW emission region. The n-type contact layer is sufficiently thin to permit a coupling of the surface plasmons (SPs) from the metal nanoparticles and the excitons in the active QW emission region. The SP-exciton coupling provides an alternative decay route for the excitons and thus enhances the photon emission from the LED device.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: July 15, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventor: Michael A. Mastro
  • Patent number: 8759812
    Abstract: According to an embodiment, a semiconductor light emitting device is configured to emit light by energy relaxation of an electron between subbands of a plurality of quantum wells. The device includes an active layer and at least a pair of cladding layers. The active layer is provided in a stripe shape extending in a direction parallel to an emission direction of the light, and includes the plurality of quantum wells; and the active layer emits the light with a wavelength of 10 ?m or more. Each of the cladding layers is provided both on and under the active layer respectively and have a lower refractive index than the active layer. At least one portion of the cladding layers contains a material having a different lattice constant from the active layer and has a lower optical absorption at a wavelength of the light than the other portion.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeyuki Takagi, Hidehiko Yabuhara
  • Patent number: 8697465
    Abstract: An LED epitaxial structure includes a substrate, a buffer layer and an epitaxial layer. The buffer layer is grown on a top surface of the substrate, and the epitaxial layer is formed on a surface of the buffer layer. The epitaxial layer has a first n-type epitaxial layer and a second n-type epitaxial layer. The first n-type epitaxial layer is formed between the buffer layer and the second n-type epitaxial layer. The first n-type epitaxial layer has a plurality of irregular holes therein.
    Type: Grant
    Filed: November 20, 2011
    Date of Patent: April 15, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang
  • Patent number: 8669546
    Abstract: A nitride group semiconductor light emitting device includes a substrate, n-type and p-type semiconductor layers, and an active region. The n-type and p-type semiconductor layers are formed on or above the substrate. The active region is interposed between the n-type and p-type semiconductor layers. The active region includes barrier layers that are included in a multiquantum well structure, and an end barrier layer that has a thickness greater than the barrier layer, and is arranged closest to the p-type semiconductor layer. The average thickness of the last two barrier layers that are arranged adjacent to the end barrier layer is smaller than the average thickness of the other barrier layers among the thicknesses of the barrier layers that are included in the multiquantum well structure.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: March 11, 2014
    Assignee: Nichia Corporation
    Inventor: Yasuhisa Kotani
  • Patent number: 8653550
    Abstract: An LED device having plasmonically enhanced emission is provided. The device includes an inverted LED structure with a coating of metal nanoparticles on the surface chosen to match the plasmonic response to the peak emission from the active quantum well (QW) emission region of the LED. The active QW emission region is separated from the metal nanoparticles on the surface by a thin n-type contact layer disposed on a top side of the active QW emission. A p-type layer is disposed immediately beneath the active QW emission region and injects holes into the active QW emission region. The n-type contact layer is sufficiently thin to permit a coupling of the surface plasmons (SPs) from the metal nanoparticles and the excitons in the active QW emission region. The SP-exciton coupling provides an alternative decay route for the excitons and thus enhances the photon emission from the LED device.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 18, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventor: Michael A. Mastro
  • Patent number: 8552445
    Abstract: A semiconductor light emitting device having high reliability and excellent light distribution characteristics is provided. Specifically, a semiconductor light emitting device 1 is provided with an n-electrode 50, which is arranged on a light extraction surface on the side opposite to the surface whereupon a semiconductor stack 40 is mounted on a substrate 10. A plurality of convexes are arranged on a first convex region 80 and a second convex region 90 on the light extraction surface. The second convex region 90 adjoins to the interface between the n-electrode 50 and the semiconductor stack 40, between the first convex region 80 and the n-electrode 50.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: October 8, 2013
    Assignee: Nichia Corporation
    Inventors: Yohei Wakai, Hiroaki Matsumura, Kenji Oka
  • Patent number: 8552457
    Abstract: A thermal stress releasing structure is applied to a light-emitting diode (LED) which includes a P-type electrode, a permanent substrate, a binding layer, a buffer layer, a mirror layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, and an N-type electrode that are stacked in sequence. The buffer layer includes a plurality of first material layers and a plurality of second material layers. The first material layers and the second material layers are alternately stacked in a staggered manner to form a concave-convex structure in a stacking direction of the first and second material layers. The concave-convex structure is formed in a corrugated shape to function as the thermal stress releasing structure, thus is capable of releasing thermal stress generated by thermal expansion and contraction of the buffer layer in the LED to prevent the buffer layer from damaging a metal layer or an epitaxy layer.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: October 8, 2013
    Assignee: High Power Opto. Inc.
    Inventors: Wei-Yu Yen, Fu-Bang Chen, Chih-Sung Chang
  • Patent number: 8405066
    Abstract: A nitride-based semiconductor light-emitting device having enhanced efficiency of carrier injection to a well layer is provided. The nitride-based semiconductor light-emitting device comprises a hexagonal gallium nitride-based semiconductor substrate 5, an n-type gallium nitride-based semiconductor region 7 disposed on the principal surface S1 of the substrate 5, a light-emitting layer 11 having a single-quantum-well structure disposed on the n-type gallium nitride-based semiconductor region 7, and a p-type gallium nitride-based semiconductor region 19 disposed on the light-emitting layer 11. The light-emitting layer 11 is disposed between the n-type gallium nitride-based semiconductor region 7 and the p-type gallium nitride-based semiconductor region 19. The light-emitting layer 11 includes a well layer 15 and barrier layers 13 and 17. The well layer 15 comprises InGaN.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: March 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Yohei Enya, Yusuke Yoshizumi, Katsushi Akita, Takamichi Sumitomo, Masaki Ueno
  • Patent number: 8357951
    Abstract: An LED (light emitting diode) chip includes a substrate, a first conduction layer formed on a top surface of the substrate, and a second conduction layer formed on the first conduction layer. The first conduction layer extends from a bottom surface of the second conduction layer to a circumferential surface of the second conduction layer, thereby surrounding the bottom surface and the circumferential surface of the second conduction layer. An active layer is sandwiched between the first and second conduction layers, to increase a contact area between the active layer and the first conduction layer and the second conduction layer.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: January 22, 2013
    Assignee: Foxsemicon Integrated Technology, Inc.
    Inventor: Kuo-Cheng Chang
  • Publication number: 20130009130
    Abstract: A laterally contacted blue LED device involves a PAN structure disposed over an insulating substrate. The substrate may be a sapphire substrate that has a template layer of GaN grown on it. The PAN structure includes an n-type GaN layer, a light-emitting active layer involving indium, and a p-type GaN layer. The n-type GaN layer has a thickness of at least 500 nm. A Low Resistance Layer (LRL) is disposed between the substrate and the PAN structure such that the LRL is in contact with the bottom of the n-layer. In one example, the LRL is an AlGaN/GaN superlattice structure whose sheet resistance is lower than the sheet resistance of the n-type GnA layer. The LRL reduces current crowding by conducting current laterally under the n-type GaN layer. The LRL reduces defect density by preventing dislocation threads in the underlying GaN template from extending up into the PAN structure.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 10, 2013
    Applicant: Bridgelux, Inc.
    Inventors: Zhen Chen, William Fenwick, Steve Lester
  • Publication number: 20120211771
    Abstract: An LED epitaxial structure includes a substrate, a buffer layer and an epitaxial layer. The buffer layer is grown on a top surface of the substrate, and the epitaxial layer is formed on a surface of the buffer layer. The epitaxial layer has a first n-type epitaxial layer and a second n-type epitaxial layer. The first n-type epitaxial layer is formed between the buffer layer and the second n-type epitaxial layer. The first n-type epitaxial layer has a plurality of irregular holes therein.
    Type: Application
    Filed: November 20, 2011
    Publication date: August 23, 2012
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: PO-MIN TU, SHIH-CHENG HUANG
  • Patent number: 8212242
    Abstract: The present invention relates to an OLED display, and an OLED display according to an exemplary embodiment of the present invention includes a substrate member, an OLED including a first electrode formed on the substrate member, an organic emission layer formed on the first electrode, and a second electrode formed on the organic emission layer, and a cover layer formed on the second electrode and covering the OLED. The cover layer includes a cover main body and a corner-cube pattern formed on an opposite side of a side that faces the second electrode among both sides of the cover main body.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: July 3, 2012
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Eun-Ah Kim, Soon-Ryong Park, Woo-Suk Jung, Hee-Chul Jeon, Noh-Min Kwak, Hee-Seong Jeong, Joo-Hwa Lee, Chul-Woo Jeong
  • Publication number: 20120161103
    Abstract: An electrically pumped optoelectronic semiconductor chip includes at least two radiation-active quantum wells comprising InGaN or consisting thereof. The optoelectronic semiconductor chip includes at least two cover layers which include AlGaN or consist thereof. Each of the cover layers is assigned to precisely one of the radiation-active quantum wells. The cover layers are each located on a p-side of the associated radiation-active quantum well. The distance between the radiation-active quantum well and the associated cover layer is at most 1.5 nm.
    Type: Application
    Filed: June 30, 2010
    Publication date: June 28, 2012
    Applicant: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Matthias Peter, Tobias Meyer, Jürgen Off, Tetsuya Taki, Joachim Hertkorn, Matthias Sabathil, Ansgar Laubsch, Andreas Biebersdorf
  • Publication number: 20120161102
    Abstract: A light emitting device is provided. The light emitting device comprises an active layer comprising a plurality of well layers and barrier layers. The barrier layers comprise a first barrier layer which is the nearest to a second conductive type semiconductor layer and has a first band gap, a second barrier layer having a third band gap, and a third barrier layer having the first band gap between the second barrier layer and a first conductive type semiconductor layer. The well layers comprise a first well layer having a second band gap between the first and the second barrier layers, and a second well layer between the second barrier layer and the third barrier layer. The second barrier layer is disposed between the first and the second well layers, and the third band gap is narrower than the first band gap and wider than the second band gap.
    Type: Application
    Filed: February 1, 2012
    Publication date: June 28, 2012
    Inventor: Jong Hak WON
  • Publication number: 20120153254
    Abstract: An LED device having plasmonically enhanced emission is provided. The device includes an inverted LED structure with a coating of metal nanoparticles on the surface chosen to match the plasmonic response to the peak emission from the active quantum well (QW) emission region of the LED. The active QW emission region is separated from the metal nanoparticles on the surface by a thin n-type contact layer disposed on a top side of the active QW emission. A p-type layer is disposed immediately beneath the active QW emission region and injects holes into the active QW emission region. The n-type contact layer is sufficiently thin to permit a coupling of the surface plasmons (SPs) from the metal nanoparticles and the excitons in the active QW emission region. The SP-exciton coupling provides an alternative decay route for the excitons and thus enhances the photon emission from the LED device.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 21, 2012
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventor: Michael A. Mastro
  • Publication number: 20120138891
    Abstract: A method for reduction of efficiency droop using an (Al, In, Ga)N/AlxIn1-xN superlattice electron blocking layer (SL-EBL) in nitride based light emitting diodes.
    Type: Application
    Filed: October 27, 2011
    Publication date: June 7, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Roy B. Chung, Changseok Han, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 8154032
    Abstract: An electrooptical device having a plurality of light-emitting regions includes a substrate, a bank disposed in a region other than the light-emitting regions on the substrate so as to surround the light-emitting regions, and a functional layer disposed in openings surrounded by the bank. The bank includes an upper bank segment and a plurality of lower bank segments having a higher wettability than the upper bank segment. The number of the lower bank segments exposed is smaller in second regions of the openings than in first regions of the openings.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: April 10, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Hirokazu Yanagihara
  • Patent number: 8134169
    Abstract: A circuit structure includes a substrate and a film over the substrate and including a plurality of portions allocated as a plurality of rows. Each of the plurality of rows of the plurality of portions includes a plurality of convex portions and a plurality of concave portions. In each of the plurality of rows, the plurality of convex portions and the plurality of concave portions are allocated in an alternating pattern.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: March 13, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Ding-Yuan Chen
  • Publication number: 20120043525
    Abstract: A light emitting device includes a substrate having a first surface and a second surface not parallel to the first surface, and a light emission layer disposed over the second surface to emit light. The light emission layer has a light emission surface which is not parallel to the first surface.
    Type: Application
    Filed: October 31, 2011
    Publication date: February 23, 2012
    Applicant: SIPHOTON INC.
    Inventor: Shaoher X. Pan
  • Publication number: 20120032140
    Abstract: A light-emitting diode (LED) (101). The LED (101) includes a plurality of portions including a p-doped portion (112), an intrinsic portion (114), and a n-doped portion (116). The intrinsic portion (114) is disposed between the p-doped portion (112) and the n-doped portion (116) and forms a p-i junction (130) and an i-n junction (134) The LED (101) also includes a metal-dielectric-metal (MDM) structure (104) including a first metal layer (140), a second metal layer (144), and a dielectric medium disposed between the first metal layer (140) and the second metal layer (144). The metal layers of the MDM structure (104) are disposed about orthogonally to the p-i junction (130) and the i-n junction (134); the dielectric medium includes the intrinsic portion (114); and, the MDM structure (104) is configured to enhance modulation frequency of the LED (101) through interaction with surface plasmons that are present in the metal layers.
    Type: Application
    Filed: September 18, 2009
    Publication date: February 9, 2012
    Inventors: Jingjing Li, David A. Fattal, Lars Helge Thylen, Michael Renne Ty Tan, Shih-Yuan Wang
  • Publication number: 20120007040
    Abstract: A light emitting device, a light emitting device package, and a lighting system are provided. The light emitting device includes a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first and second conductive type semiconductor layers. The active layer includes a first active layer adjacent to the second conductive type semiconductor layer, a second active layer adjacent to the first conductive type semiconductor layer, and a gate quantum barrier between the first and second active layers.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 12, 2012
    Inventors: Yong Tae MOON, Jeong Sik Lee, Dae Seob Han
  • Publication number: 20110284821
    Abstract: The embodiment relates to a light emitting device and a light emitting device package, wherein the light emitting device includes a first conduction type semiconductor layer, an active layer formed on the first conduction type semiconductor layer, and a second conduction type semiconductor layer formed on the active layer, wherein the active layer includes a quantum well layer and a quantum barrier layer, and a face direction lattice constant of the first conduction type semiconductor layer or the second conduction type semiconductor layer is greater than the face direction lattice constant of the quantum barrier layer and smaller than the face direction lattice constant of the quantum well layer.
    Type: Application
    Filed: December 27, 2010
    Publication date: November 24, 2011
    Inventors: Yong Tae MOON, Jeong Sik LEE, Joong Seo PARK, Ho Ki KWON, Seoung Hwan PARK
  • Publication number: 20110278534
    Abstract: An optoelectronic device that includes a material having enhanced electronic transitions. The electronic transitions are enhanced by mixing electronic states at an interface. The interface may be formed by a nano-well, a nano-dot, or a nano-wire.
    Type: Application
    Filed: February 22, 2011
    Publication date: November 17, 2011
    Inventor: Marcie R. Black
  • Publication number: 20110266520
    Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.
    Type: Application
    Filed: June 17, 2011
    Publication date: November 3, 2011
    Inventors: Michael Shur, Remigijus Gaska, Jinwei Wang
  • Publication number: 20110227035
    Abstract: Provided is a nitride-based semiconductor light-emitting element having improved carrier injection efficiency into the well layer. The element comprises a substrate (5) formed from a hexagonal-crystal gallium nitride semiconductor; an n-type gallium nitride semiconductor region (7) disposed on a main surface (S1) of the substrate (5); a light-emitting layer (11) having a single quantum well structure disposed on the n-type gallium nitride semiconductor region (7); and a p-type gallium nitride semiconductor region (19) disposed on the light-emitting layer (11). The light-emitting layer (11) is disposed between the n-type gallium nitride semiconductor region (7) and the p-type gallium nitride semiconductor region (19). The light-emitting layer (11) comprises a well layer (15), a barrier layer (13), and a barrier layer (17). The well layer (15) is InGaN.
    Type: Application
    Filed: June 14, 2010
    Publication date: September 22, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi Kyono, Yohei Enya, Yusuke Yoshizumi, Katsushi Akita, Takamichi Sumitomo, Masaki Ueno
  • Publication number: 20110210312
    Abstract: A semiconductor light-emitting device includes a substrate, a buffer layer, an n-type semiconductor layer, a conformational active layer and a p-type semiconductor layer. The n-type semiconductor layer includes a first surface and a second surface, and the first surface directly contacts the buffer layer. The second surface includes a plurality of recesses, and a conformational active layer formed on the second surface and within the plurality of recesses. Widths of upper portions of the recesses are larger than widths of lower portions of the recesses. Therefore, the stress between the n-type semiconductor layer and the conformational active layer can be released with the recesses.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 1, 2011
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Po Min Tu, Shih Cheng Huang, Ying Chao Yeh, Wen Yu Lin, Peng Yi Wu, Chih Peng Hsu, Shih Hsiung Chan
  • Patent number: 7952109
    Abstract: An apparatus comprising a structure comprising a group III-nitride and a junction between n-type and p-type group III-nitride therein, the structure having a pyramidal shape or a wedge shape.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: May 31, 2011
    Assignee: Alcatel-Lucent USA Inc.
    Inventor: Hock Min Ng
  • Publication number: 20110108744
    Abstract: A photon source comprising: a quantum dot; electrical contacts configured to apply an electric field across said quantum dot: and an electrical source coupled to said contacts, said electrical source being configured to apply a potential such that carriers are supplied to said quantum dot to form a bi-exciton or higher order exciton, wherein said photon source further comprises a barrier configured to increase the time which a carrier takes to tunnel to and from said quantum dot to be greater than the radiative lifetime of an exciton in the quantum dot, the quantum dot being suitable for emission of entangled photons during decay of a bi-exciton or higher order exciton.
    Type: Application
    Filed: October 13, 2010
    Publication date: May 12, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Richard Mark Stevenson, Andrew James Shields
  • Patent number: 7781796
    Abstract: A nitride semiconductor laser element includes a substrate and a nitride semiconductor layer in which a first semiconductor layer, an active layer, and a second semiconductor layer are laminated in this order on the substrate. At least one of the first semiconductor layer and the second semiconductor layer includes a first section forming recessed and raised portions and a second section embedding the recessed and raised portions of the first section. A region with a higher aluminum mixed crystal ratio than the second section that embeds the recessed and raised portions is disposed on top faces of the raised portions. The nitride semiconductor layer defines resonant planes, and the recessed and raised portions are formed in a shape of stripes that extend substantially parallel to the resonant planes.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: August 24, 2010
    Assignee: Nichia Corporation
    Inventors: Shingo Masui, Kazutaka Tsukayama
  • Patent number: 7700936
    Abstract: In one embodiment, a method of producing an optoelectronic nanostructure includes preparing a substrate; providing a quantum well layer on the substrate; etching a volume of the substrate to produce a photonic crystal. The quantum dots are produced at multiple intersections of the quantum well layer within the photonic crystal. Multiple quantum well layers may also be provided so as to form multiple vertically aligned quantum dots. In another embodiment, an optoelectronic nanostructure includes a photonic crystal having a plurality of voids and interconnecting veins; a plurality of quantum dots arranged between the plurality of voids, wherein an electrical connection is provided to one or more of the plurality of quantum dots through an associated interconnecting vein.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 20, 2010
    Assignee: University of Delaware
    Inventors: Janusz Murakowski, Garrett Schneider, Dennis W. Prather
  • Patent number: 7652295
    Abstract: A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 26, 2010
    Assignees: LG Innotek Co., Ltd., LG Electronics Inc.
    Inventors: Hyun Kyong Cho, Sun Kyung Kim, Jun Ho Jang
  • Patent number: 7633093
    Abstract: An optical light engine is fabricated by providing a thermally conductive base having one or more mounting pedestals for elevating one or more LED die above the base's surface. The LED die are mounted on the pedestals, electrically connected, and a mold having a molding surface for molding a dome centered around the LED die is disposed on the base over the pedestal-mounted LED die. The encapsulating material is then injected through an input port disposed in the base to mold the dome around the LED die. The encapsulant material is cured and the mold is removed. In an advantageous embodiment, the light engine comprises a ceramic-coated metal base made by the low temperature co-fired ceramic-on-metal process (LTCC-M).
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: December 15, 2009
    Assignee: Lighting Science Group Corporation
    Inventors: Greg Blonder, Shane Harrah
  • Publication number: 20090166606
    Abstract: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.
    Type: Application
    Filed: December 5, 2005
    Publication date: July 2, 2009
    Inventor: Suk Hun Lee
  • Patent number: 7550775
    Abstract: A GaN semiconductor light-emitting element is provided. The GaN semiconductor light-emitting element includes an island-type seed region composed of a GaN-based compound semiconductor disposed on a substrate; an underlying layer having a three-dimensional shape composed of a GaN-based compound semiconductor, disposed on at least the seed region; a first GaN-based compound semiconductor layer of a first conductivity type, an active layer composed of a GaN-based compound semiconductor, and a second GaN-based compound semiconductor layer of a second conductivity type disposed in that order on the underlying layer; a first electrode electrically connected to the first GaN-based compound semiconductor layer; and a second electrode disposed on the second GaN-based compound semiconductor layer. The top face of the seed region is the A plane, and at least one side face of the underlying layer is the S plane.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: June 23, 2009
    Assignee: Sony Corporation
    Inventor: Hiroyuki Okuyama
  • Publication number: 20090029493
    Abstract: Light emitting devices include an active region comprising a plurality of layers and a pit opening region on which the active region is disposed. The pit opening region is configured to expand a size of openings of a plurality of pits to a size sufficient for the plurality of layers of the active region to extend into the pits. In some embodiments, the active region comprises a plurality of quantum wells. The pit opening region may comprise a superlattice structure. The pits may surround their corresponding dislocations and the plurality of layers may extend to the respective dislocations. At least one of the pits of the plurality of pits may originate in a layer disposed between the pit opening layer and a substrate on which the pit opening layer is provided. The active region may be a Group III nitride based active region. Methods of fabricating such devices are also provided.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 29, 2009
    Inventors: David Todd Emerson, Michael John Bergmann
  • Publication number: 20060131593
    Abstract: A semiconductor laser element capable of reducing the contact resistance and the thermal resistance and realizing a high reliability is provided. The semiconductor laser element includes: a semiconductor substrate, an active layer formed on the semiconductor substrate, a ridge having a clad layer formed on the active layer and a contact layer formed on the clad layer, an insulation film covering the side surfaces of the clad layer, and an electrode connected to the contact layer, wherein the insulation layer has an end portion in the ridge thickness direction located between the upper surface and the lower surface of the contact layer.
    Type: Application
    Filed: February 9, 2006
    Publication date: June 22, 2006
    Inventors: Haruki Fukai, Hidetaka Karita, Atsushi Nakamura, Shigeo Yamashita
  • Patent number: 7029936
    Abstract: A semiconductor laser element capable of reducing the contact resistance and the thermal resistance and realizing a high reliability is provided. The semiconductor laser element includes: a semiconductor substrate, an active layer formed on the semiconductor substrate, a ridge having a clad layer formed on the active layer and a contact layer formed on the clad layer, an insulation film covering the side surfaces of the clad layer, and an electrode connected to the contact layer, wherein the insulation layer has an end portion in the ridge thickness direction located between the upper surface and the lower surface of the contact layer.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: April 18, 2006
    Assignees: Hitachi, Ltd., Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Haruki Fukai, Hidetaka Karita, Atsushi Nakamura, Shigeo Yamashita