Including Porous Si (epo) Patents (Class 257/E33.018)
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Publication number: 20120119187Abstract: The present invention relates to a GaN based nitride based light emitting device improved in Electrostatic Discharge (ESD) tolerance (withstanding property) and a method for fabricating the same including a substrate and a V-shaped distortion structure made of an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer on the substrate and formed with reference to the n-type nitride semiconductor layer.Type: ApplicationFiled: January 25, 2012Publication date: May 17, 2012Applicant: SAMSUNG LED CO., LTDInventors: Sang Won KANG, Yong Chun KIM, Dong Hyun CHO, Jeong Tak OH, Dong Joon KIM
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Patent number: 8148234Abstract: A method for manufacturing a semiconductor structure is provided which includes the following operations: supplying a crystalline semiconductor substrate, providing a porous region adjacent to a surface of the semiconductor substrate, introducing a dopant into the porous region from the surface, and thermally recrystallizing the porous region into a crystalline doping region of the semiconductor substrate whose doping type and/or doping concentration and/or doping distribution are/is different from those or that of the semiconductor substrate. A corresponding semiconductor structure is likewise provided.Type: GrantFiled: March 9, 2007Date of Patent: April 3, 2012Assignee: Robert Bosch GmbHInventors: Gerhard Lammel, Hubert Benzel, Matthias Illing, Franz Laermer, Silvia Kronmueller, Paul Farber, Simon Armbruster, Ralf Reichenbach, Christoph Schelling, Ando Feyh
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Patent number: 7829913Abstract: A structure of a substrate used for growing a crystal layer of a semiconductor, particularly a group-III nitride semiconductor and its manufacturing method. The substrate comprises two porous layers on a base. The mean opening diameter of the pores of the first porous laser, the outermost layer, is smaller than the means diameter of the pores in the second porous layer nearer to the base than the first porous layer. The first and second porous layers have volume porosities of 10 to 90%. More then 50% of the pores of the first porous layer extend from the surface of the first porous layer and reach the interface between the first and second porous layers. Even by a conventional crystal growing method, an epitaxial crystal of low defect density can be easily grown on the porous substrate.Type: GrantFiled: June 26, 2003Date of Patent: November 9, 2010Assignees: Hitachi Cable, Ltd., NEC CorporationInventors: Masatomo Shibata, Yuichi Oshima, Takeshi Eri, Akira Usui, Haruo Sunagawa
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Patent number: 7759139Abstract: A method for manufacturing a silicon device includes steps of: forming a silicon layer 4a that indicates a second conductivity type on a first surface S1a of a silicon substrate 2a that indicates a first conductivity type; and exposing, after the step, a third surface S3a of the silicon layer 4a for a period of a minimum of 30 minutes and a maximum of 6 hours to an argon-containing atmosphere which is adjusted to temperatures of a minimum of 400° C. and a maximum of 900° C. and pressures of a minimum of 4 MPa and a maximum of 200 MPa.Type: GrantFiled: August 22, 2007Date of Patent: July 20, 2010Assignee: Hamamatsu Photonics K.K.Inventors: Shucheng Chu, Hirofumi Kan
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Patent number: 7700936Abstract: In one embodiment, a method of producing an optoelectronic nanostructure includes preparing a substrate; providing a quantum well layer on the substrate; etching a volume of the substrate to produce a photonic crystal. The quantum dots are produced at multiple intersections of the quantum well layer within the photonic crystal. Multiple quantum well layers may also be provided so as to form multiple vertically aligned quantum dots. In another embodiment, an optoelectronic nanostructure includes a photonic crystal having a plurality of voids and interconnecting veins; a plurality of quantum dots arranged between the plurality of voids, wherein an electrical connection is provided to one or more of the plurality of quantum dots through an associated interconnecting vein.Type: GrantFiled: June 30, 2006Date of Patent: April 20, 2010Assignee: University of DelawareInventors: Janusz Murakowski, Garrett Schneider, Dennis W. Prather
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Patent number: 7582906Abstract: A lighting device surface-emits light from a light emitting surface of a light emitting element and guides the emitted light using a light guide member. The lighting device has a first wavelength conversion member for converting light emitted from the light emitting device into light having a first peak wavelength and a second wavelength conversion member for converting light emitted from the light emitting device into light having a wavelength shorter than the first peak wavelength. The first wavelength conversion member is provided between the light emitting element and the light guide member and is contained in a resin potting the light emitting element. A film has a layer containing the second wavelength conversion member. The film is provided on a light emitting surface side of the light guide member.Type: GrantFiled: March 8, 2007Date of Patent: September 1, 2009Assignee: Seiko Instruments Inc.Inventor: Makoto Kurihara
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Patent number: 7531423Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.Type: GrantFiled: December 22, 2005Date of Patent: May 12, 2009Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack Allan Mandelman, Haining Yang
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Patent number: 7468529Abstract: A filter for trapping, sterilizing, and decomposing organic matter, bacteria, viruses, and other harmful substances is provided at low cost and extremely high efficiency. A semiconductor material having a light emitting function is formed in the interior or on the surface of a porous ceramic material substrate by deposition from a suspension of semiconductor particles, and an electrode provided to serve as a filter. Voltage is applied so that ultraviolet light is emitted while a fluid is being filtered, and any harmful substances are filtered and simultaneously sterilized and decomposed.Type: GrantFiled: July 10, 2003Date of Patent: December 23, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Chihiro Kawai, Masami Tatsumi
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Patent number: 7327036Abstract: The present invention is related to a device comprising a substrate comprising a silicon substrate having a porous top layer, a second layer on said top layer, said second layer made of a material comprising Ge, and a further layer of a Group III-nitride material on the second layer. The present invention further is related to methods of production and to intermediate or template devices highly suitable for the epitaxial growth of a high quality Group III-nitride layer.Type: GrantFiled: December 21, 2004Date of Patent: February 5, 2008Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Gustaaf Borghs, Stefan Degroote, Marianne Germain
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Patent number: 7309620Abstract: The invention relates to methods for preparing a removable system on a mother substrate. The method deposits a high surface to volume sacrificial layer on a mother substrate and stabilizes the sacrificial layer by a) removing volatile chemical species in and on the sacrificial layer and/or b) modifying the surface of the layer. The method coats over the sacrificial layer with a capping medium. A system is the fabricated on the capping medium. The method provides through holes to access the sacrificial layer. The method may also apply a top layer onto the system to form a covered system. The invention also includes the step of removing the sacrificial layer to release the system from the mother substrate. Methods of the invention also include selectively removing a portion of the system and capping layers to form void regions defining an array of islands composed of device, structure, or system and capping layer regions, and optionally filling the island-defining void region with a sacrificial material.Type: GrantFiled: January 13, 2003Date of Patent: December 18, 2007Assignee: The Penn State Research FoundationInventors: Stephen J. Fonash, Handong Li, Youngchul Lee, Joseph D. Cuiffi, Daniel J. Hayes
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Publication number: 20060138394Abstract: A minute structure is provided in which electroconductive paths are only formed in nanoholes, and a material is filled in the nanoholes, which are disposed in a specific area, by using the electroconductive paths.Type: ApplicationFiled: February 16, 2006Publication date: June 29, 2006Applicant: CANON KABUSHIKI KAISHAInventors: Tohru Den, Tatsuya Iwasaki