Comprising High Tc Ceramic Materials (epo) Patents (Class 257/E39.015)
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Patent number: 11900214Abstract: Methods and apparatus for enhancing simulated annealing with quantum fluctuations. In one aspect, a method includes obtaining an input state; performing simulated annealing on the input state with a temperature reduction schedule until a decrease in energy is below a first minimum value; terminating the simulated annealing in response to determining that the decrease in energy is below the first minimum level; outputting a first evolved state and first temperature value; reducing the temperature to a minimum temperature value; performing quantum annealing on the first evolved state with a transversal field increase schedule until a completion of a second event occurs; terminating the quantum annealing in response to determining that a completion of the second event has occurred; outputting a second evolved state as a subsequent input state for the simulated annealing, and determining that the completion of the first event has occurred.Type: GrantFiled: August 4, 2021Date of Patent: February 13, 2024Inventor: Hartmut Neven
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Patent number: 11528541Abstract: Concepts and technologies directed to optical networking with hybrid optical vortices are disclosed herein. Embodiments can include a system that is configured to perform operations for optical networking with hybrid optical vortices. The system can include a hybrid optical switch that can communicatively couple with another network device via one or more nanofiber communication paths. The operations can include receiving, from a first nanofiber communication path, a hybrid optical vortex that carries an internet protocol packet. The operations also can include decoupling the hybrid optical vortex to extract an optical vortex that encapsulates the internet protocol packet. The operations also can include switching the internet protocol packet to a subsequent communication path based on the optical vortex that encapsulates the internet protocol packet.Type: GrantFiled: October 4, 2021Date of Patent: December 13, 2022Assignee: AT&T Intellectual Property I, L.P.Inventors: Timothy Innes, Oliver Elliott, Samuel Scruggs
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Patent number: 8766384Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.Type: GrantFiled: October 30, 2012Date of Patent: July 1, 2014Assignee: QUALCOMM IncorporatedInventor: Xia Li
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Patent number: 8680592Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped.Type: GrantFiled: May 14, 2010Date of Patent: March 25, 2014Assignee: QUALCOMM IncorporatedInventor: Xia Li
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Patent number: 7755165Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.Type: GrantFiled: January 10, 2008Date of Patent: July 13, 2010Assignee: Intel CorporationInventors: Cengiz A. Palanduz, Dustin P. Wood
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Patent number: 7544964Abstract: A method for producing a thin layer device such as a superconductive device excellent in mechanical strength and useful as a submillimeter band receiver is provided. The thin layer device is produced by forming a multilayer structure substance comprising an NbN/MgO/NbN-SIS junction on an MgO temporary substrate, then forming SiO2, as a substrate, on said multilayer structure substance, and subsequently removing the MgO temporary substrate by etching. A superconductive device (a thin layer device) produced by a method of the present invention has excellent performance and high mechanical strength, and therefore introduction to a waveguide for a submillimeter band is also easy.Type: GrantFiled: September 25, 2006Date of Patent: June 9, 2009Assignee: National Institute of Information and Communications Technology, Incorporated Administrative AgencyInventor: Akira Kawakami
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Patent number: 7449769Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having Josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having Josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.Type: GrantFiled: May 30, 2006Date of Patent: November 11, 2008Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical FoundationInventor: Tsunehiro Hato
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Publication number: 20080051292Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Inventors: Hironori Wakana, Seiji Adachi, Koji Tsubone, Keiichi Tanabe