Beam Lead Frame Or Beam Lead Device Patents (Class 29/827)
  • Patent number: 11968916
    Abstract: A method of maintaining artificial turf using a turf maintenance robot. The artificial turf comprises an artificial turf carpet, wherein the artificial turf carpet comprises turf fibers which form an artificial turf surface. The artificial turf fibers have a grain. The artificial turf comprises artificial turf infill distributed between the artificial turf fibers. The turf maintenance robot is a self-driving robot, wherein the turf maintenance robot comprises a memory for storing turf grain data, descriptive the grain of the artificial turf fibers. The method comprises brushing the artificial turf surface by the turf maintenance robot. The turf maintenance robot performs the brushing dependent upon the turf grain data.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: April 30, 2024
    Assignee: Melos GmbH
    Inventor: Jorg Siekmann
  • Patent number: 11908705
    Abstract: A method for aligning interconnects that includes trimming and forming a frame of strips of interconnects. The frame of strips of interconnects includes interdigitated pins. The method also includes removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects. The method includes aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects. A strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects. The method further includes singulating the aligned array of strips of interconnects.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: February 20, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Chih-Chien Ho
  • Patent number: 11903319
    Abstract: The present invention is directed to improving an insulating property of a backing in which a lead array is buried. The method includes a coating forming process, in which insulating coatings are formed with respect to at least a plurality of lead rows included in a plurality of lead frames; after the forming of the insulating coatings, a plate manufacturing process, in which a plurality of backing plates are manufactured by pouring a backing material towards a lead row in each of the plurality of lead frames so that the lead row and the backing material are integrated with each other; and a laminating process, in which the plurality of backing plates are laminated.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: February 13, 2024
    Assignee: FUJIFILM Healthcare Corporation
    Inventors: Hidetsugu Katsura, Yoshihiro Tahara, Kazuhiro Kobayashi
  • Patent number: 11837573
    Abstract: A chip bonding apparatus includes: a bonding contact configured to apply a bonding force to a semiconductor chip disposed on a substrate, the bonding contact having a first surface configured to face the semiconductor chip and a second surface opposite the first surface, the bonding contact including a protruding portion on the first surface, the protruding portion configured to contact the semiconductor chip, the bonding contact including a cavity formed in a region vertically overlapping the protruding portion, a heater disposed to be in contact with the second surface of the bonding contact to cover the cavity, and configured to heat the bonding contact, a bonding head disposed above the heater and configured to transmit the bonding force, and a partition wall structure protruding from a bottom surface of the cavity to partition an inner space of the cavity.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhyung Kim, Joongha Lee, Sangha Park, Sunghyup Kim, Kyeongbin Lim
  • Patent number: 11735509
    Abstract: Provided are a power semiconductor device using a lead frame, in which deformation and bending of terminals is suppressed, insulation is secured between terminals, and mounting onto a control board is facilitated, and a manufacturing method thereof. A package in which a semiconductor element mounted on a lead frame is sealed, terminals being bent and exposed from side surfaces of the package, and, a terminal bending portion being a portion bent in each of the terminals, a width thereof being larger than a width of a tip of the terminal, and being equal to or smaller than the width of a contact portion of the terminal in contact with the package are provided; therefore, deformation and bending of the terminals is suppressed, a necessary insulation is secured between the adjacent terminals, and mounting onto a control board is facilitated.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: August 22, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keitaro Ichikawa, Taketoshi Shikano, Yuji Shikasho, Fumihito Kawahara
  • Patent number: 11670558
    Abstract: A semiconductor device includes a semiconductor element, a die pad, an encapsulating member, and a plurality of leads. The die pad has a front surface on which the semiconductor element is mounted. The encapsulating member covers and seals the semiconductor element. The plurality of leads each have a first end connected to the semiconductor element in an inside of the encapsulating member and a second end led out from a side surface of the encapsulating member. A lower surface of a package including the semiconductor element, the die pad, and the encapsulating member is located on a back surface side of the die pad and has a convexly curved shape.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 6, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masafumi Jochi
  • Patent number: 11600951
    Abstract: The present invention relates to methods and systems for minimizing alien crosstalk between connectors. Specifically, the methods and systems relate to isolation and compensation techniques for minimizing alien crosstalk between connectors for use with high-speed data cabling. A frame can be configured to receive a number of connectors. Shield structures may be positioned to isolate at least a subset of the connectors from one another. The connectors can be positioned to move at least a subset of the connectors away from alignment with a common plane. A signal compensator may be configured to adjust a data signal to compensate for alien crosstalk. The connectors are configured to efficiently and accurately propagate high-speed data signals by, among other functions, minimizing alien crosstalk.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 7, 2023
    Assignee: CommScope Technologies LLC
    Inventor: Bernard Harold Hammond, Jr.
  • Patent number: 11424564
    Abstract: A connector includes a rectangular flat-plate housing including a first positioning hole and a second positioning hole, and a contact row and a contact row held on the housing. The housing includes a first pitch side surface and a second pitch side surface on an opposite side of the first pitch side surface. The contact row and the contact row extend from the first pitch side surface to the second pitch side surface. The first positioning hole is disposed between the first pitch side surface and the contact row, and the second positioning hole is disposed between the first pitch side surface and the contact row.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: August 23, 2022
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventors: Junji Oosaka, Yuichi Takenaga, Akihiro Matsunaga
  • Patent number: 11398451
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry. Substrates employed to provide the memory die and the support die can be reused by replacing one of the substrates with an alternative low-cost substrate that provides structural support to the bonded assembly.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 26, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Raghuveer S. Makala, Peter Rabkin
  • Patent number: 11367973
    Abstract: A connector includes a rectangular flat-plate housing including a first positioning hole and a second positioning hole, and a contact row and a contact row held on the housing. The housing includes a first pitch side surface and a second pitch side surface on an opposite side of the first pitch side surface. The contact row and the contact row extend from the first pitch side surface to the second pitch side surface. The first positioning hole is disposed between the first pitch side surface and the contact row, and the second positioning hole is disposed between the first pitch side surface and the contact row.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: June 21, 2022
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventors: Junji Oosaka, Yuichi Takenaga, Akihiro Matsunaga
  • Patent number: 11348793
    Abstract: A laser processing apparatus has a laser beam applying unit for applying a laser beam to a workpiece held on a chuck table. The laser beam applying unit includes an elliptical spot forming member for changing the spot shape of a pulsed laser beam into an elliptical shape and making the major axis of the elliptical beam spot parallel to a feeding direction, a diffractive optical element for branching the pulsed laser beam having the elliptical beam spot obtained by the elliptical spot forming member, into a plurality of pulsed laser beams each having an elliptical beam spot whose major axis extends in the feeding direction, and a condensing lens for condensing each of the pulsed laser beams branched by the diffractive optical element to the workpiece in such a manner that the major axes of the elliptical beam spots of the pulsed laser beams branched are partially overlapped.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 31, 2022
    Assignee: DISCO CORPORATION
    Inventor: Yuta Yoshida
  • Patent number: 11302485
    Abstract: A capacitor unit includes a capacitor having a positive electrode and a negative electrode, a positive bus bar, a negative bus bar, a sealing resin, an insulator. The positive bus bar and the negative bus bar are respectively connected to the positive electrode and the negative electrode. The sealing resin seals the capacitor, a part of the positive bus bar, and a part of the negative bus bar. The insulator is located between the positive bus bar and the negative bus bar. The insulator includes a recess recessed from either surface of the insulator facing the positive bus bar or the negative bus bar. At least a part of the recess is exposed from the sealing resin.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 12, 2022
    Assignee: DENSO CORPORATION
    Inventors: Yuya Kiuchi, Kenshiro Hida
  • Patent number: 11267062
    Abstract: Systems and methods are disclosed that may include identifying a first coefficient of thermal expansion for a first component, the first component including component pins having a first pitch value; identifying a second coefficient of thermal expansion for a second component, the second component associated with electrically conductive pads; determining a relative expansion value based on the first coefficient of thermal expansion and the second coefficient of thermal expansion; determining a change in temperature value of the first component and the second component, the change in temperature value indicating a change in temperature caused by a soldering process; and determining a second pitch value for the electrically conductive pads based on a product of the relative expansion value, the first pitch value, and the change in temperature value, the second pitch value causing an alignment between the component pins and the electrically conductive pads during the soldering process.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: March 8, 2022
    Assignee: Dell Products L.P.
    Inventors: Brian D. Kennedy, Stephen E. Strickland
  • Patent number: 11270971
    Abstract: A semiconductor device capable of suppressing propagation of a crack caused by a temperature cycle at a bonding part between a bonding pad and a bonding wire is provided. A semiconductor device according to an embodiment includes a semiconductor chip having bonding pads and bonding wires. The bonding pad includes a barrier layer and a bonding layer formed on the barrier layer and formed of a material containing aluminum. The bonding wire is bonded to the bonding pad and formed of a material containing copper. An intermetallic compound layer formed of an intermetallic compound containing copper and aluminum is formed so as to reach the barrier layer from the bonding wire in at least a part of the bonding part between the bonding pad and the bonding wire.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: March 8, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenji Ikura, Hideki Ishii, Takehiko Maeda, Takeumi Kato
  • Patent number: 11220127
    Abstract: A method of processing sheet stock in the creation of plastic cards, such as gift cards or credit cards that include special effects and/or security measures. A card formed by such methods is also disclosed. The method provides for two or more dissimilar materials to be bonded together while maintaining the integrity of the card and as any graphics, security features, and/or special effects provided thereon. Thermoset and thermobond adhesive layers are placed between a first material layer and a second material layer of the sheet stock. The thermoset and thermobond adhesive layers allow the first and second material layers to move independently and to expand and contract at different rates relative to each other. The adhesive layers enable the sheet stock to be rolled up for shipping or storage and further enable the end product produced therefrom to have a planar profile.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 11, 2022
    Assignee: Griff and Associates, L.P.
    Inventor: Timothy Roche
  • Patent number: 11172574
    Abstract: A printed circuit board assembly includes a first printed circuit board, a second printed circuit board, and a space holding member. The second printed circuit board includes a first rigid substrate region, spaced apart from and opposed to the first printed circuit board, and a flexible substrate region, extended from one side of the first rigid substrate region to be connected to the first printed circuit board. The space holding member includes a first member, disposed between the first printed circuit board and the second printed circuit board to maintain a space therebetween, and a second member configured to fix the first printed circuit board or the second printed circuit board on the first member.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: November 9, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae-Ho Shin, Jun-Oh Hwang, Yun-Je Ji, Tae-Seong Kim
  • Patent number: 11139268
    Abstract: A semiconductor package structure includes a substrate, a first semiconductor die, a first dielectric, a second semiconductor die, and a second dielectric. The substrate has a first surface. The first semiconductor die is disposed on the first surface. The first dielectric encapsulates the first semiconductor die. The second semiconductor die is disposed on the first surface and adjacent to the first semiconductor die. The second dielectric encapsulates the second semiconductor die. The first dielectric is in contact with the second dielectric. An average filler size in the first dielectric is substantially greater than an average filler size in the second dielectric.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11059207
    Abstract: Provided is a method for producing a composite member formed by bonding a base material and a resin member. The method includes: a surface treatment step of forming micro-order or nano-order asperities on a surface of a base material; and a bonding step of directly bonding, by injection molding, a resin member to the surface of the base material that has the asperities formed in the surface treatment step. In addition, the composite member includes: a base material having micro-order or nano-order asperities on a surface thereof; and a resin member that is in direct contact with the surface of the base material.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: July 13, 2021
    Assignees: The University of Tokyo, The Foundation for the Promotion of Industrial Science
    Inventors: Yusuke Kajihara, Fuminobu Kimura, Yuta Tamura, Naotake Nakura, Eiji Yamaguchi, Norihito Shibuya
  • Patent number: 11025126
    Abstract: A brushed DC motor includes a motor shell, a stator fixed within the motor shell, an armature rotor rotatably disposed inside the motor shell and surrounding by the stator while forming a gap therebetween with magnetic field, and a brush cap connected with the motor shell by covering an installing opening of the motor shell. The brush cap includes a base layer, an electric circuit layer formed on the base layer, at least one pair of brush frames affixed thereon symmetrically, and at least one pair of brushes respectively installed in the brush frames and electrically connected with the electric circuit layer adapted to receive current and conduct to the armature rotor for driving an output end of the armature rotor to rotate with respect to the stator.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 1, 2021
    Assignee: NETMOTOR (U.S.A.) INC.
    Inventor: Guobin Wang
  • Patent number: 11004756
    Abstract: A semiconductor device includes: a base plate; a semiconductor chip mounted on the base plate; a case surrounding the semiconductor chip on the base plate; an electrode terminal connected to the semiconductor chip; a sealing material covering an upper face of the base plate, the semiconductor chip and a part of the electrode terminal in the case; and a lid fastened to the case above the sealing material, wherein the electrode terminal is not exposed on an upper face of the sealing material, and there is a gap between the upper face of the sealing material and a lower face of the lid.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: May 11, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kota Ohara, Manabu Matsumoto, Yoshitaka Otsubo
  • Patent number: 10999917
    Abstract: A aesthetically appealing mounting system for an electronic device capable of forming a semi-conductive path for electro-static discharge. The mounting system can include an electrically conductive layer covered by a cosmetic anodized layer with multiple micro-perforations formed through the anodized layer exposing a small portion of the electrically conductive layer. The micro-perforations can be formed by laser-etching the cosmetic anodized layer to provide a grounding path while the micro-perforations remain visually undetectable. A semi-conductive wear layer can be configured to couple with the anodized layer. In some embodiments, the semi-conductive wear layer is in a recess on an electronic device. In some embodiments, the semi-conductive wear layer is comprised of a conformal conductive rubber.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 4, 2021
    Assignee: Apple Inc.
    Inventors: Rhett D. Gentile, Peter N. Jeziorek, Sunita Venkatesh, Lauren M. Farrell, Steven J. Osborne
  • Patent number: 10980115
    Abstract: Embodiments of the disclosure are directed to a harness assembly including a substrate having a plurality of vias, and a trace formed atop the substrate, the trace extending between each of the plurality of vias. The harness assembly may further include a surface mounted device disposed within a via of the plurality of vias.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: April 13, 2021
    Assignee: Littelfuse, Inc.
    Inventors: Yuriy B. Matus, Martin G. Pineda, Werner Johler, Brad A. Benson
  • Patent number: 10978626
    Abstract: A display apparatus includes a plurality of unit modules; and a cover configured to support the plurality of unit modules. Each of the plurality of unit modules includes: a substrate; a plurality of inorganic light emitting diodes provided on a mounting surface of the substrate; and an encapsulation layer formed on the mounting surface of the substrate to cover the plurality of inorganic light emitting diodes and the mounting surface of the substrate. The encapsulation layer includes a viscoelastic material having varying viscoelasticity based on temperature being applied to the viscoelastic material.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Soon Park, Tack Mo Lee, Jung Hoon Yoon
  • Patent number: 10960488
    Abstract: A method for operating an ultrasonic wire bonder. The ultrasonic wire bonder has a bonding head with a bonding tool and with a transducer for exciting ultrasonic vibrations in the bonding tool and a controller (2) for the transducer (1). In a first process phase I a bonding wire is bonded to a substrate. The bonding wire is pressed against the substrate with a bonding force via a tool tip of the bonding tool, and the bonding tool is then excited so as to undergo ultrasonic vibrations in order to produce a bond between the bonding wire and the substrate, the transducer (1) being excited so as to vibrate for a specified or variable bonding time. In a second process phase II, the actuation of the transducer (1) is changed and reverberations of the bonding tool are counteracted, the transducer (1) being operated in a damped manner.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: March 30, 2021
    Assignee: Hesse GmbH
    Inventors: Matthias Hunstig, Michael Broekelmann
  • Patent number: 10821553
    Abstract: A method of cutting a polarizing plate by using a laser, and a polarizing plate cut using the same. A beam shape of the laser is configured to have an elliptical shape and a major axis of the elliptical shape parallel to a cutting direction to provide excellent cross-sectional quality and improved productivity.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 3, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Beom Seok Lee, Eung Jin Jang, Sukjae Lee, Kyoung Sik Kim
  • Patent number: 10796818
    Abstract: The present specification relates to a heating element and a method for manufacturing the same.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: October 6, 2020
    Assignee: LG CHEM., LTD.
    Inventors: Ji Eun Myung, Sera Kim, Jooyeon Kim, Chang Yoon Lim, Seung Heon Lee, Mun Seop Song, Kwang Joo Lee, Ji Young Hwang
  • Patent number: 10770205
    Abstract: A method for manufacturing an electronic component including a step of providing an outer electrode that includes a step of providing a sintered layer containing a sintered metal, a step of providing an insulation layer containing an electric insulation material, and a step of providing a Sn-containing layer containing Sn. The sintered layer extends from each of end surfaces of an element assembly onto at least one main surface thereof. The insulation layer is directly provided on the sintered layer at each of the end surfaces so as to extend in a direction perpendicular or substantially perpendicular to a side surface of the element assembly, and defines a portion of a surface of the outer electrode. The Sn-containing layer covers the sintered layer except for a portion of the sintered layer that is covered by the insulation layer, and constitutes another portion of the surface of the outer electrode.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: September 8, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Haruhiko Mori, Hiroyuki Otsuna
  • Patent number: 10746786
    Abstract: A method for producing, on a metal retainer plate, an electronic module undergoing an electrical test. Prior to a final overmolding that forms the exterior envelope of the electronic module, there is performed a limited initial overmolding of at least one electrical-connection zone, thus surrounding a free-end portion of a rough form of an insulating second securing bar, by establishing between these a non-conducting overmolded bridge, a first securing bar is cut off from a component or element in order to electrically isolate said at least one electrical-connection zone, and an electrical test is performed on the zone prior to the final overmolding of the exterior envelope, with the electronic component or element being secured to the insulating second securing bar and to the retainer plate by the overmolded bridge.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: August 18, 2020
    Assignees: Continental Automotive France, Continental Automotive GmbH
    Inventors: Hervé Contet, Martin Throm, Dietmar Huber
  • Patent number: 10741515
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 11, 2020
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 10699992
    Abstract: An electronic assembly that includes a substrate having an aperture which extends through the substrate. The electronic assembly further includes a gull wing electronic package that includes leads which are solder mounted to the substrate such that the gull wing electronic package is within the aperture in the substrate, wherein the aperture is concentric with an exterior of the gull wing electronic package.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Juan Landeros, Jason M. Seitz, Mingjing Huang
  • Patent number: 10583579
    Abstract: A field-pole magnet manufacturing apparatus fractures a magnet fixed on a die serving as a lower tool by causing a punch of an upper tool to press the magnet while in contact with the magnet. At least one projection is formed in the punch of the upper tool symmetrically with respect to the central position of the magnet in the width direction of the magnet.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: March 10, 2020
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Kazuhiro Takaichi, Kimio Nishimura, Hiroharu Takeuchi, Kunitomo Ishiguro, Kiyoshi Hasegawa, Yasuhisa Koike
  • Patent number: 10551011
    Abstract: A method for manufacturing a lighting assembly is disclosed, wherein a light emitting diode (LED) element (120) is arranged on a leadframe (110). The LED element (120) is configured to emit light when supplied with electrical power by means of the leadframe (110). At least a portion of the leadframe (110) is provided with an optically reflective and electrically insulating material (130) arranged to reflect light emitted from the LED element (120) and to electrically insulate at least a portion of the leadframe (110). A lighting assembly comprising the LED element (120) and the leadframe (110) is also disclosed.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: February 4, 2020
    Assignee: Lumileds LLC
    Inventors: Peter Henri Bancken, Bas Fleskens
  • Patent number: 10541225
    Abstract: A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng @ Eugene Lee, Wei Fen Sueann Lim, Anis Fauzi Bin Abdul Aziz
  • Patent number: 10506721
    Abstract: An electronic module card with bypass capacitor includes a main board, an adhesive layer and a conduction skirting board. The main board has an inserting section and a plurality of solder pads disposed on a soldering region of the inserting section. At least one solder pad has a first extending part extending therefrom. The conduction skirting board is fixed to the inserting section, and has a rigid substrate and a plurality of conductive pads. Each conductive pad has an outer contacting part, and an adapting part. A gap is formed between the conduction skirting board and the main board. At least one conductive pad has a second extending part extended from the adapting part along an inner surface of the rigid substrate. A part of the second extending part is partially overlapped above a part of the first extending part so as to form a bypass capacitor.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 10, 2019
    Inventor: Sung-Yu Chen
  • Patent number: 10431530
    Abstract: A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 1, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Si Hyeon Go, Jun Young Heo, Moon Taek Sung, Dong Seong Oh
  • Patent number: 10242961
    Abstract: A semiconductor device includes: an insulating substrate including an insulating plate and a circuit board on the insulating plate; a semiconductor chip having an electrode on a front surface thereof, a back of the semiconductor chip being fixed to the circuit board; a printed circuit board that faces the circuit board and the front surface of the semiconductor chip; and one or more conductive posts each having one end connected via solder to the circuit board or to the electrode on the semiconductor chip, another end connected to the printed circuit board, and one or more grooves that extend from said one end of the conductive post that contacts the solder to said another end of the conductive post connected to the printed circuit board.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: March 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichiro Hinata
  • Patent number: 10050387
    Abstract: A method for manufacturing a shielded connector includes: providing a body having an upper surface, a lower surface, a signal accommodating hole and a ground accommodating hole; plating a metal layer on the upper surface of the body and inner walls of the signal accommodating hole and the ground accommodating hole; forming an isolating region in the area around the signal accommodating hole to divide the metal layer into a first metal layer and a second metal layer; electrifying the first metal layer with an electroplating treatment so as to increase a thickness of the first metal layer, where the second metal layer is not thickened; partially removing the metal layer, so as to completely remove the second metal layer and decrease the thickness of the first metal layer; and installing a signal terminal and a ground terminal correspondingly in the signal accommodating hole and the ground accommodating hole, respectively.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 14, 2018
    Assignee: LOTES CO., LTD
    Inventors: Yong Quan Wu, Chien Hung Ho, You Hua Cai, Zuo Feng Jin, Chang Wei Huang
  • Patent number: 9852961
    Abstract: A packaged semiconductor device includes a semiconductor component, first and second heat dissipation means disposed between the semiconductor component and the first and second main faces, respectively, encapsulated by an encapsulant, the shape of the packaged semiconductor device being non-rectangular cuboid.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies AG
    Inventor: Chong Yee Tong
  • Patent number: 9831609
    Abstract: Electrical connector includes a connector body and a plurality of electrical contacts coupled to the connector body. Each of the electrical contacts has an elongated body that includes a base material and an impedance-control material plated over the base material. The impedance-control material extends along only a designated portion of the elongated body. The impedance-control material has a relative magnetic permeability that is greater than a relative magnetic permeability of the base material. The impedance-control material increasing an impedance of the electrical contact along the designated portion.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: November 28, 2017
    Assignees: TE CONNECTIVITY CORPORATION, TYCO ELECTRONICS JAPAN G.K.
    Inventors: Masayuki Aizawa, Chad William Morgan
  • Patent number: 9805956
    Abstract: Disclosed is a method of manufacturing a lead frame, which comprises the steps of: providing an electrically-conductive base material having first and second planar sides; forming a plurality of conductive contact points on the first planar side of the base material; providing a non-conductive filling material over the first planar side of the base material so that the filling material fills spaces in-between the plurality of contact points to a form a layer comprising the filling material and the plurality of contact points; and etching the second planar side of the base material to expose a pattern of the filling material from the second planar side of the base material and to thereby form a plurality of isolated conductive regions on the second planar side of the base material, each isolated conductive region being connected with at least a respective one of the plurality of contact points on the first planar side of the base material. A lead frame structure is also disclosed.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: October 31, 2017
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Dawei Xing, Jie Liu, Hong Wei Guan, Yue Gen Yu, Seow Kiang Khoo
  • Patent number: 9756730
    Abstract: A laminate and method for producing the laminate are provided for contacting at least one electronic component. An insulating layer is laminated between first and second metal layers electrically contacted to each other in at least one contact region. At least one recess in the contact region is generated with at least one embossing and/or bulging in the first metal layer. The distance between the two metal layers is reduced, such that dimensions of the embossing/bulging are sufficient for taking up the electronic component, which is inserted and connected into the embossing/bulging in a conductive manner therein. The electronic component is taken up in the embossing/bulging entirely with respect to its circumference and at least partly with respect to the height (H) of the electronic component. The laminate may be used as a circuit board, sensor, LED lamp, mobile phone component, control, or regulator.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 5, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Andreas Steffen Klein, Eckhard Ditzel, Frank Krüger, Michael Schumann
  • Patent number: 9748721
    Abstract: A method of fabricating connector terminals, includes (a) preparing a single electrically conductive metal sheet including a plurality of pre-terminals, and a plurality of carriers connecting adjacent pre-terminals to each other, each of the pre-terminals having at one end thereof in a length-wise direction thereof an elastically deformable contact portion, and at the other end in the length-wise direction a first area, a pitch between adjacent contact portions being unequal to a pitch between adjacent first areas, (b) folding each of the first areas around a line extending in a length-wise direction thereof to thereby form a male tab having a predetermined thickness, and (c) removing the carriers out of the metal sheet.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 29, 2017
    Assignee: DAI-ICHI SEIKO CO., LTD.
    Inventors: Takayoshi Endo, Masaya Muta
  • Patent number: 9711455
    Abstract: A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Elbert E. Huang, Dimitri R. Kioussis, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 9637377
    Abstract: The present invention relates to a method for forming a micro-surface structure on a substrate, in particular for producing a micro-electromechanical component, a micro-surface structure of this type, a method for producing a micro-electromechanical component having a micro-surface structure of this type and such a micro-electromechanical component. The invention is particularly relevant for components of microsystem technology (MST, micro-electromechanical systems MEMS) and the construction and connection technology for hermetically housing micro components, preferably using getter materials.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: May 2, 2017
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.
    Inventors: Wolfgang Reinert, Jochen Quenzer, Kai Gruber, Stephan Warnat
  • Patent number: 9616223
    Abstract: Media-exposed interconnects for transducer modules are disclosed. The transducers may be sensing transducers, actuating transducers, IC-only transducers, or combinations thereof, or other suitable transducers. The transducers may be used in connection with implantable medical devices and may be exposed to various media, such as body fluids. The media-exposed interconnects for transducer modules may allow transducers to communicate electrically with other components, such as implantable medical devices.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 11, 2017
    Assignee: Medtronic, Inc.
    Inventors: Michael A. Schugt, Kamal D. Mothilal, David A. Ruben, Lary R. Larson, Michael F. Mattes
  • Patent number: 9508665
    Abstract: A method for insertion bonding and a device thus obtained are disclosed. In one aspect, the device includes a first substrate having a front main surface and at least one protrusion at the front main surface. The device includes a second substrate having a front main surface and at least one hole extending from the front main surface into the second substrate. The protrusion of the first substrate is inserted into the hole of the second substrate. The hole is formed in a shape wherein the width is reduced in the depth direction and wherein the width of at least a part of the hole is smaller than the width of the protrusion at the location of the metal portion thereof. The protrusion is deformed during insertion thereof in the hole to provide a bond between the part of the hole and the metal portion.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: November 29, 2016
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventors: Eric Beyne, Paresh Limaye
  • Patent number: 9472427
    Abstract: A semiconductor device has a leadframe with first and second opposing surfaces and a plurality of notched fingers. The leadframe is mounted to a carrier. A first semiconductor die is mounted over the carrier between the notched fingers. Conductive TSVs are formed through the first semiconductor die. A bond wire is formed between a first contact pad on the first semiconductor die and notched finger. The conductive TSV are electrically connected to the bond wires. An encapsulant is deposited over the first semiconductor die and notched fingers. Bumps are formed over the first surface of the leadframe. The carrier is removed and the leadframe is singulated. The leadframe and first semiconductor die is mounted to a substrate. A second semiconductor die is mounted to a second contact pad on the first semiconductor die. A third semiconductor die is mounted to the second surface of the leadframe.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: October 18, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
  • Patent number: 9455207
    Abstract: Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate. According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 27, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kwang Soo Kim, Si Joong Yang, Bum Seok Suh, Young Hoon Kwak, Job Ha
  • Patent number: 9416002
    Abstract: A method for assembling a packaged semiconductor device includes mounting a pressure-sensing die onto a die paddle of a metal lead frame. A pressure-sensitive gel is dispensed into a recess of a lid, and the lead frame is mated with the lid such that the pressure-sensing die is immersed in the pressure-sensitive gel within the recess of the lid.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: August 16, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Nan Xu, Xingshou Pang, Xuesong Xu
  • Patent number: 9393785
    Abstract: A flexible cable includes a portion that is covered by a solder resist and an exposed portion that is not covered by the solder resist, in which the exposed portion contains a wiring terminal and at least continues to a position closer to an outside than an opening of a wiring member insertion side of a wiring vacant portion in a state in which the wiring terminal portion is connected to an element terminal of a piezoelectric element side and in which the wiring vacant portion is filled with an electrically insulating filling material in a state of covering a joining portion between the element terminal and the wiring terminal within the wiring vacant portion, and in a state in which a protective substrate, which forms the wiring vacant portion by partitioning, and the exposed portion of the flexible cable are not in contact with one another.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: July 19, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Ryota Kinoshita, Hiroaki Okui, Shunsuke Watanabe, Hitoshi Yamada, Tadao Furuta