Abstract: A True Single Phase Clock (TSPC) pre-charge based flip-flop is provided. The flip-flop includes a scan section, a master section, and a slave section. The scan section receives a scan enable signal, a scan input signal, a clock signal, and feedback data from the master section, and outputs an internal signal to the master section based on the scan enable signal, the scan input signal, the clock signal, and the feedback data. The master section is coupled to the scan section and receives the internal signal and a data input, and outputs a master feedback signal to the slave section based on the internal signal, the data input, and the feedback data. The slave section is coupled to the master section and generates an output by latching the master feedback signal received from the master section according to the clock signal. The clock signal is a True-Single-Phase-Clock (TSPC).

Abstract: A data reading device and a data reading method for design-for-testing are provided. The data reading device includes a buffer and a data serialization circuit. The data serialization circuit receives a clock positive edge-triggered signal, a clock negative edge-triggered signal, a trigger mask signal, and test data. The data serialization circuit masks one of the clock positive edge-triggered signal and the clock negative edge-triggered signal according to the trigger mask signal, and provides a part of the test data to an output terminal of the data serialization circuit as an output signal of the data reading device according to the unmasked one of the clock positive edge-triggered signal and the clock negative edge-triggered signal. Thus, a data valid window of the test data can be increased.

Abstract: A logic gate device is disclosed. The logic gate device structure can include a magnetic tunnel junction on a soft ferromagnetic wire to provide a readout. One input contact can be at one end of the soft ferromagnetic wire and a second input contact can be at the other end of the soft ferromagnetic wire to control domain wall position in the soft ferromagnetic wire.

Abstract: Disclosed is an improved noise reducing apparatus using an anti-circuit, including a digital logic circuit and a digital anti-circuit corresponding to the digital logic circuit. The digital anti-circuit functions to cancel noise generated by the digital logic circuit. The anti-circuit includes logic to generate a similar number of switching edges as the logic circuit, where the anti-circuit edges are in the opposite direction as the logic circuit. The anti-circuit may have a circuit structure close to that of the noisy circuit, or can be formed of components different in structure but generating an output pattern similar to (and opposite from) the noisy circuit. In some embodiments, the differently structured components can include a state machine coupled to a memory or look-up-table.

Abstract: A driving apparatus for a display device includes a gray voltage generator that generates a plurality of gray voltage sets, each including a plurality of gray voltages having different levels, and a signal converter that includes a first selector for selecting one gray voltage set among the plurality of gray voltage sets on the basis of a first portion of an image signal and a second selector for selecting one or more gray voltages among the plurality of gray voltages belonging to the selected gray voltage set on the basis of a second portion of the image signal to output and select gray voltages with a smaller size digital-analog converter.

Abstract: In a voltage dividing circuit, a first circuit where only a first switch is connected, a second circuit where a first resistor and a second switch are connected in series, a third circuit where a second resistor and a third switch are connected in series and a fourth circuit where a third resistor and a fourth switch are connected in series are connected in parallel. One end of the parallel circuit is connected to a limit resistor and the other end of the parallel circuit is connected to a ground point. One switch is provided between a connecting point in one circuit and a connecting point in another circuit, and each resistor of at least two circuits is connected in parallel by said one switch.

Abstract: Disclosed is an improved noise reducing apparatus using an anti-circuit, including a digital logic circuit and a digital anti-circuit corresponding to the digital logic circuit. The digital anti-circuit functions to cancel noise generated by the digital logic circuit. The anti-circuit includes logic to generate a similar number of switching edges as the logic circuit, where the anti-circuit edges are in the opposite direction as the logic circuit. The anti-circuit may have a circuit structure close to that of the noisy circuit, or can be formed of components different in structure but generating an output pattern similar to (and opposite from) the noisy circuit. In some embodiments, the differently structured components can include a state machine coupled to a memory or look-up-table.

Abstract: A method for operating a magnetic logic device (10) is described wherein at least one output variable O=F (IA, IB) is formed from input variables (IA, IB) by at least one logic operation with an operator function F of the magnetic logic device (10), whereby the logic device (10) is set at a starting state for executing the operator function F with a certain operator control signal (SET) before the operation, whereby the operator control signal is selected from a group of control signals with which various non-volatile starting states can be set in a controlled manner, each state being characteristic of a different logic function. Furthermore, a magnetic logic device (10) equipped for implementation of this method is also described.

Abstract: An apparatus having n-number of working cross-connects for cross-connecting an n-bit input signals arriving from a plurality of input paths on a per-bit basis; n-number of first logic circuits for calculating the exclusive-ORs of each said n-bit and applying outputs to a standby cross-connect for providing outputs; n-number of second logic circuits for calculating the exclusive-ORs of said output signals from each of said working cross-connects and from the single standby cross-connect; and third logic circuits for selecting output signals of said working cross-connects and outputs of the second logic circuits. The apparatus detects the occurrence of an abnormality in working cross-connects by monitoring the outputs of the second logic circuits, identifies the faulty cross-connect by successively turning off one of the n-inputs to the first and second logic circuits, and select outputs from the second logic circuits instead of from the faulty cross-connect by using the third logic circuits.

Abstract: A divided multiplexer structure which can be used to replace a tristate bus, comprising node elements which are embodied in such a way that no feedback can occur in between the interconnected nodes. For this purpose, each node includes at least one feedback-free connection port.

Abstract: Previously in a bus system, voltage signals were transmitted from the central unit to the modules, which could reply thereto by variation of the current input. A disadvantage thereby is the relatively high susceptibility to interference of the current input, which itself already must be kept relatively small due to the energy consumption, as well as the correspondingly high effort and expense for an error-free recognition of the signals transmitted from the modules in the central unit. It is now suggested, that the modules also answer to the central unit by means of voltage signals superposed on the direct supply voltage, whereby for the time duration of the signal transmission by the modules, the central unit provides the direct supply voltage to the bus line over a resistor, so that the voltage signal of the module can be detected in the central unit on the bus line on the side of the resistor facing away from the direct supply voltage.

Abstract: A voltage drop compensating reactor connected between the power distribution system and the load provides a flux shifting multiple-winding reactor with a capacitor bank connected between the reactor windings. At least one line winding is oriented in a first polarity on a core, and at least one compensating winding oriented in the opposite polarity on the core and connected between the output of the first winding and the load. The opposing fluxes generated by the line winding and the compensating winding cancel and the total reactance of the device is lower than the reactance of the line winding. The input of a cross-link circuit comprising a capacitor is connected between the line winding and the compensating winding. The reactance through the cross-link circuit to the neutral (or another phase) is lower than the reactance through the line winding.

Abstract: A method and an apparatus reduce peak electro-magnetic (EM) emissions from power and ground planes in, for example, a printed circuit board (PCB) by phase shifting synchronous signal sources to distribute EM emissions over a frequency range and by canceling at least some EM emissions with an inverse signal. According to one aspect of the present invention, two signal sources provide periodic outputs having the same period. The output of one of the signal sources, however, is delayed with respect to the output of the other signal source. Each signal source is coupled to a signal trace. The propagation delay over the signal trace coupled to the delayed signal source is shorter than the propagation delay over the other signal trace by the amount of the delay between the respective output signals. According to another aspect of the present invention, a noise cancellation driver is coupled to a signal source, a power or ground plane of the signal source, and an inverse voltage plane.

Abstract: A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.

Abstract: A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.

Abstract: A logic circuit is described. The logic circuit generates a first signal state in response to a first set of input signals, generates a second signal state in response to a second set of input signals, activates a bypass switch in response to the first signal state, and bypasses a domino logic unit in response to the first signal state.

Abstract: A test system for a digital integrated circuit in which internal states of the integrated circuit are captured non-destructively while the digital circuit is operating at normal clock speed. Cells for capturing states are sequentially connected into shift registers. Once internal states are latched within cells, the captured states are serially shifted out a test port while the integrated circuit continues to operate. State sampling is triggered internally via a software command or externally via an external signal synchronized to an internal clock.

Abstract: Timing restrictions for coincidence of control and data signal pulses to a soliton-based optical logic device are significantly relaxed by predistorting a characteristic of data signal pulses input to the device. Predistortion in the form of normal dispersion is sufficient to cause each predistorted data signal pulse to change shape subsequently in the optical logic device and thereby permit effective interaction between the data signal pulses and the control pulses to achieve the desired result of the logic operation. The temporal separation between control and data signal pulses has been extended to cover a total range of up to four pulse widths without degrading the operation of the optical logic device.

Abstract: An optical logic device based on the time-shift-keying architecture is described in which digital logic functions are realized by applying appropriate signal pulses to a nonlinear shift or "chirp" element whose output is supplied to a dispersive element capable of supporting soliton propagation. In an optical fiber realization of the optical logic device, two orthogonally polarized pulses are supplied to the combination of a moderately birefringent fiber acting as the nonlinear chirp element and a polarization maintaining fiber acting as the soliton dispersive delay element having a anomolous group velocity dispersion at the signal wavelengths of interest. A nonlinear frequency shift is created in one of the pulses in the former element through cross-phase modulation and, in turn, the frequency shift is translated into a temporal shift of the affected pulse in the latter element. These devices operate at switching energies approaching 1pJ.

Abstract: An optical AND gate for use in a cross-bar arithmetic/logic unit including first and second optical substrates which are configured adjacent to one another with each of the optical substrates having a respective plurality of optical paths formed thereon. The pattern of optical paths form a plurality of intersecting regions where the optical paths associated with one of the optical substrates overlaps the optical paths associated with the other optical substrate. The optical substrates are operable for transmitting an incident light beam there through so as to produce an output at one of the intersecting regions. The optical substrates transmit the incident light beam only through the optical paths which have been illuminated by a plurality of light sources.

Abstract: An optical device includes a 50-50 cross-coupler having a pair of ports optically coupled by a waveguide which includes a portion of material having a non-linear refractive index with a relaxation time such that the effect on the non-linear portion of a first pulse passing through the portion last long enough to affect the phase of a second pulse relative to the first. It finds application as a logic element, optical amplifier modulator and the like.

Abstract: Dynamic logic units utilize magnetic cores of rectangular hysteresis loop material wound with an input winding, a pair of output windings connected to a CMOS flip-flop, and a d-c control winding. With a d-c current on the control winding, the core experiences flux reversals in response to a square wave on the input winding to generate output pulses which alternately switch the flip-flop to produce a square wave output which matches the input. In a first embodiment, the output windings are in the form of a center-tapped winding with the center tap grounded to provide a low impedance discharge path for the capacitors in grounded R-C filters on the inputs to the flip-flop which suppress voltage spikes. In a second embodiment, output windings on separate magnetic cores which share an input windings but only one of which has a control winding, are connected in opposition to eliminate the switching spikes in the signal applied to the flip-flop.

Abstract: An AND function gating circuit for A.C. signals comprising several magnetic circuits around a common limb, each circuit having a separate input winding and a single output winding on the common limb. The magnetic flux level in the common limb is greatly increased when all input windings are simultaneously energized by A.C. signals of the same frequency and in phase relative to the output achieved under other input signal conditions.