Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Abstract: The present disclosure provides an OLED display substrate, its manufacturing method and a display device. The OLED display substrate includes a base substrate, and a TFT and an OLED driven by the TFT on the base substrate and. The OLED includes, in a direction away from the base substrate, an anode, an organic layer and a cathode in turn. The OLED display substrate further includes an auxiliary electrode connected in parallel to a part of the cathode.

Abstract: Method and Apparatuses for of transmitting data between semiconductor chips are described. An example apparatus includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes first and second inductors. The first semiconductor chip transmits a first combination of a plurality of data bits in logical value by flowing a first current through the first inductor and by flowing substantially no current through the second inductor. The second semiconductor chip includes third and fourth inductors that correspond respectively to the first and second inductors of the first semiconductor chip. The second semiconductor chip receives the first combination of the plurality of data bits in logical value by detecting an electromotive force at the third inductor responsive to the first current and by detecting substantially no electromotive force at the fourth inductor responsive to no current.

Abstract: A protection switching circuit includes a plurality of ferrite modules arranged in a matrix, wherein the matrix includes a plurality of columns and a plurality of rows. The protection switching circuit further includes a primary control module configured to select a specific ferrite module to be polarized and a redundant control module configured to select a specific ferrite module to be polarized, wherein the redundant control module is used when the primary control module is not used. The protection switching circuit further includes a plurality of first switches, wherein the plurality of first switches couples the plurality of columns of the matrix to a first and second charging circuit. The protection switching circuit further includes a plurality of second switches, wherein the plurality of second switches are organized into pairs, wherein each pair in the plurality of second switches couples a respective row of the matrix to a reference potential.

Abstract: A method and device for generating a power supply voltage (Vf), referenced to a first reference potential (4), in an electronic system including an energizing source (3) connected to the first and second reference potentials (4, 5) so as to impart an AC voltage differential between the reference potentials (4, 5), wherein the device includes: (i) a source (10) for supplying AC voltage, which is referenced to the second reference potential (5), connected to the first reference potential (4), and encompasses the energizing source (3); and (ii) rectifying and filtering elements (1) connected, at the input thereof, to the first reference potential (4) and to the source (10) for supplying AC voltage, respectively, so as to generate, at an output (8), a power supply voltage (Vf) referenced to the first reference potential (4) by rectifying a voltage at the terminals of the source (10) for supplying AC voltage.

Abstract: In a first inductive structure, a first data coil includes: a first portion for conducting a first common mode current in a first direction; and a second portion for conducting a second common mode current in a second direction opposite the first direction. The first and second portions of the first data coil are connected at a first node. In a second inductive structure, a second data coil includes: a first portion for conducting a third common mode current in the first direction; and a second portion for conducting a fourth common mode current in the second direction. The first and second portions of the second data coil are connected at a second node galvanically isolated from the first node. The first, second, third and fourth common mode currents are induced by a common mode transient.

Abstract: When a direction command signal indicates a first direction, a signal for causing the other end of the induction load to be connected to a second power supply unit is output as a second control signal. In addition, after a passage of a first predetermined delay time after a first current detection value becomes less than a reference value of a conducting current, a signal for causing the one end of the induction load 5 to be connected to a first power supply unit is output as a first control signal. And, after a passage of a second predetermined delay time after the first current detection value becomes equal to or greater than the reference value of the conducting current, a signal for causing the one end of the induction load to be connected to the second power supply unit is output as the first control signal.

Abstract: A linear transformer driver includes at least one ferrite ring positioned to accept a load. The linear transformer driver also includes a first power delivery module that includes a first charge storage devices and a first switch. The first power delivery module sends a first energy in the form of a first pulse to the load. The linear transformer driver also includes a second power delivery module including a second charge storage device and a second switch. The second power delivery module sends a second energy in the form of a second pulse to the load. The second pulse has a frequency that is approximately three times the frequency of the first pulse. The at least one ferrite ring is positioned to force the first pulse and the second pulse to the load by temporarily isolating the first pulse and the second pulse from an electrical ground.

Abstract: The invention relates to a power transmission system for transmitting electrical power from a power source to a load. The system comprises a capacitive and lossy transmission line or cable and a transformer device. The transformer device comprises a magnetic core and a first winding wound around a first axis of the magnetic core. The first end of the transmission line or cable is connected to the power source and the second end of the transmission line is connected to the transformer device. A second winding wound around the first axis of the magnetic core, where the second winding is connected to the load. A control winding is wound around a second axis of the magnetic core, where the first axis and the second axis are orthogonal axes to that when the first winding, the second winding and/or the control winding are energized, orthogonal fluxes are generated in the magnetic core.

Abstract: The present invention relates to adjustment of interconnect power levels in high-speed differential serial links. In an example embodiment, a digital signal received at a digital input port is converted in a driver into a corresponding differential signal and provided to output ports connected to a differential transmission line for provision to a receiver. For adjusting the interconnect power levels between the driver and the receiver a voltage regulator is interposed between a voltage source and the driver. The voltage regulator provides regulated supply voltage to the driver. In operation, the voltage regulator receives from control circuitry a control signal indicative of a predetermined regulated voltage for provision to the driver for a pre-selected type of data transmission. In dependence upon the received control signal the voltage regulator selects the corresponding reference voltage and provides it to the driver.

Abstract: This invention relates to a self power-acquiring quickly responsive controllable reactor whose coil of the main body portion contains a control winding (6), a net-side winding (5), further contains a tertiary winding (7). The tertiary winding (7), the control winding (6) and the net-side winding (5) are set in turn on a magnetic conductive core column of the main body portion (1) from inside to outside; the net-side winding (5) has power-acquiring taps; which connect with the primary coil of rectiformer in a rectifying-filtering unit (2). The output terminals of the rectifying-filtering unit (2) connect with the control winding (6). A quick switch (K) is in parallel connected with the tertiary winding (7). The on/off state of the quick switch (K) is controlled by the command transmitted by the control unit (4) in the controllable reactor.

Abstract: In an induction motor group control system, magnetic energy recovery switches (3) are connected in series to an induction motor (2) directly driven by a commercial power supply, and a plurality of induction motor control devices (10) enabling voltage control and reactive power control of the induction motor 2 are employed to control generation of reactive power so as to maximize a power factor of the entire plurality of AC loads including the induction motor or compensate variations in voltage of an AC power supply (1).

Abstract: In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.

Abstract: A method and a system for controlling the operation of an energizer which delivers energy to a fence in the form of a succession of pulses, the energy or waveshape of each pulse is varied in a manner which is dependent on the amount of energy which is lost by the fence for at least one pulse which is applied to the fence.

Abstract: In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.

Abstract: This invention relates to a self power-acquiring quickly responsive controllable reactor whose coil of the main body portion contains a control winding (6), a net-side winding (5), further contains a tertiary winding (7). The tertiary winding (7), the control winding (6) and the net-side winding (5) are set in turn on a magnetic conductive core column of the main body portion (1) from inside to outside; the net-side winding (5) has power-acquiring taps; which connect with the primary coil of rectiformer in a rectifying-filtering unit (2). The output terminals of the rectifying-filtering unit (2) connect with the control winding (6). A quick switch (K) is in parallel connected with the tertiary winding (7). The on/off state of the quick switch (K) is controlled by the command transmitted by the control unit (4) in the controllable reactor.

Abstract: The invention relates to a power transmission system for transmitting electrical power from a power source to a load. The system comprises a capacitive and lossy transmission line or cable and a transformer device (10). The transformer device comprises a magnetic core and a first winding wound around a first axis of the magnetic core. The first end of the transmission line or cable is connected to the power source and the second end of the transmission line is connected to the transformer device. A second winding wound around the first axis of the magnetic core, where the second winding is connected to the load. A control winding is wound around a second axis of the magnetic core, where the first axis and the second axis are orthogonal axes to that when the first winding, the second winding and/or the control winding are energized, orthogonal fluxes are generated in the magnetic core.

Abstract: A transformer controller for a drive isolation transformer is provided. The transformer may include multiple sets of primary windings as an input, and the transformer controller may include multiple branches coupled between a power source and the transformer. Each branch may be coupled to its own primary winding on the transformer, and may include one or more components, such as an isolation switch, a fuse, contactor, or circuit breaker. One or more of the branches may include a pre-charge reactor to limit inrush or capacitor charging current occurring during startup, and may include a pre-charge contactor to remove the pre-charge reactor from the circuit when the startup process has reached a certain level (e.g., the charging or inrush current has dissipated, or a DC bus reaches a charged state).

Abstract: A drive circuit for a switching circuit has a high-side drive circuit to turn on/off, according to a control signal, a switching element QH arranged on a high side of a DC power source Vin and a low-side drive circuit to turn on/off alternately with the switching element QH according to the control signal a switching element QL arranged on a low side of the DC power source and connected in series with the switching element QH. Ends of an auxiliary power source Vcc1 are connected in series with a switch element Qn1, a capacitor C1, and a switch element Qn2. Both ends of the capacitor C1 are connected in series with a switch element Qp1, a capacitor C2, and a switch element Qp2. A control circuit alternately turns on/off the switch elements Qn1 and Qn2 and the switch elements Qp1 and Qp2. The capacitor C2 provides the high-side drive circuit with source power.

Abstract: A system. The system includes a multi-winding device having a primary winding and a plurality of three-phase secondary windings, and a plurality of power cells. Each power cell is connected to a different three-phase secondary winding of the multi-winding device. The system also includes a first contact connected to a first input terminal of at least one of the power cells, a second contact connected to a second input terminal of the at least one of the power cells, and a third contact connected to first and second output terminals of the at least one of the power cells.

Abstract: A drive control circuit (100) performs drive control of a plurality of loads (111, 112) having different operating characteristics. The drive control circuit includes a plurality of connectors (106, 107) for connecting with the plurality of loads, a control portion (101) that supplies drive control signals to the plurality of loads via first electrodes of the plurality of connectors, and a comparing portion (110) that compares certain characteristic values at second electrodes concerning certain characteristics of signals applied to the first electrodes of the plurality of connectors and supplies a result of the comparison to the control portion, so that the drive control signals are decided in accordance with the result of the comparison.

Abstract: An apparatus and method used to charge a self powered gate driver system. The apparatus may include a current loop for inducing a current in a coil. A bridge rectifier may rectify the current induced in the coil and charge a capacitor used to power a driver in a self powered gate driver system. The current loop and coil may be separated by a dielectric to prevent current from passing between the self powered gate driver system and the current loop. The current loop may couple to a line voltage transformer to drive an alternating current through the current loop. In certain embodiments, a single current loop and transformer may charge a plurality of self powered gate driver systems.

Abstract: A ferrite load driver system in accordance with the invention includes a clock generator configured to generate a digital clock signal. The system further includes a digital pulse generator configured to generate an enable pulse having a pulse width equal to a certain number of clock cycles of the digital clock signal. The enable pulse is received by a driver element of the system. The driver element responds by driving a current in a first direction through the ferrite load for setting a first magnetic flux.

Abstract: Coil structures and isolators using them. A coil(s) is (are) used as a magnetic field-generating element(s) paired with another coil(s) or other magnetic field-receiving element(s). The coil(s) is(are) formed in or on a substrate which does not include some or all of the driver (i.e., input) or receiver (i.e., output) circuits. The coil(s) and magnetic field-receiving element(s) thus can be manufactured separately from the driver and/or receiver circuitry, using different processes, instead of subjecting the chip areas containing both input and output circuits to post processing to form the coil(s). Isolators can be assembled using such coils with a resultant lower cost. Isolators also can be assembled using transformers made from such coils wherein the transformers can be driven on either of their windings in order to provide bi-directional isolation with a single transformer.

Abstract: A combined output driver for TMDS signals and LVDS signals. First and second output drivers output first and second differential signals to a first external input unit and a second external input unit, respectively, through a pair of signal lines according to first and second input signals. In the second output driver, a driver buffer is coupled to a first voltage and a first node respectively to generate two control signals according to the second input signals. An output unit generates the second differential signal according to the two control signals. A power supply provides a second voltage higher than the first voltage to power the driver buffer and the output unit when the first output driver outputs the first differential signal to the first external input unit.

Abstract: A circuit of interface between a logic sensor and a logic input isolation barrier of a processing circuit, including an element of protection against input overvoltages, a current-limiting circuit connected in series between an input terminal and an output terminal of the interface circuit, and a control stage connected in parallel with the galvanic isolation element to be controlled to control the logic states thereof, the control stage inhibiting the operation of the galvanic isolation element if the input current is smaller than a predetermined threshold.

Abstract: A control system and method for controlling operation of a group of linear solenoids, which in turn control operation of an electrical load such as a solenoid or actuator, that exhibits increased responsiveness to a change in the target linear solenoid load current. A microcomputer cyclically generates and outputs pulse-width-modulated drive signals based on acquired drive data to establish clock periods. A switch connected between the microcomputer and the target load switchably connects the target load to a power source based on the drive data to selectively drive the target load. A feedback loop between the target load and the microcomputer provides actual target load drive data to the microcomputer, and the microcomputer adjusts the drive signals at a rate of not more than two times per cycle based on the actual drive data to converge the actual drive data to a calculated target load drive value.

Abstract: A high-speed switching circuit with a low or zero inductance shunt resistor is constructed using a trace resistor having parallel overlying trace portions on opposite plane faces of a printed circuit board. The resulting shunt resistor is used in combination with a detector to input data to a microcontroller which controls an automotive load device such as a blower motor. The traces which form the resistor may be extended by horizontal or vertical zig-zag folding or a combination of the two.

Abstract: A non-optical isolator having a driver circuit for providing an input signal to one or more first passive components which are coupled across a galvanic isolation barrier to one or more corresponding second passive components, and an output circuit that converts the signal from the second passive components to an output signal corresponding to the input signal. The entire structure may be formed monolithically as an integrated circuit on one or two die substrates, for low cost, small size, and low power consumption. The passive components may be coils or capacitor plates, for example. When the first and second passive components are capacitor plates, a Faraday shield may be provided between them, with the first and second passive components being referenced to separate grounds and the Faraday shield referenced to the same ground as the second passive components.

Abstract: The present invention discloses a power supply device, particularly for supplying a controlled electrical signal in an electrochemical process, e.g., plating, etching, etc. The power delivery device provides an electrical signal with optimal characteristics and setting for processing one or more surfaces in an electrochemical process. The power delivery device comprises a power stage having an input for receiving a power signal and an output being operably connected to the object. A sensor is operably connected to the output. A controller is operably connected to the output and responsive to the sensor. A modulator is operably connected between the controller and the power stage wherein the power stage outputs the electrical signal to the object in response to the modulator and the controller.

Abstract: A connector integrates a transformer and a “phantom” power provision, thus enabling a reduction in size along with an increase in versatility for electronic communication. The transformer may comprise a pair of magnetic transformers. The power source may be connected to center taps of the magnetic transformers for providing a bias voltage to the connector.

Abstract: A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.

Abstract: The invention relates to a method of handling faults and preventing damage to or from machine tools, production machines, and robots, having individually driven machine elements. Process information is exchanged between the drives (A1-A6) via at least one data link (AB1, AB2, LB, Q), with the result that a drive braking function and/or a system standstill is initiated after detection of a faulty drive (A1-A6), and the actual values (G1, G2, of the faulty drive (A1-A6) are transmitted as nominal values to the faultlessly operating drives (A1-A6) involved.

Abstract: The reader/writer of this invention includes a high voltage withstanding amplifier, plural resonance circuits and plural high voltage withstanding analog switching circuits. The high voltage withstanding amplifier amplifies an analog signal to be sent to the outside. Each of the resonance circuits sends the analog signal amplified by the high voltage withstanding amplifier to the outside. The high voltage withstanding analog switching circuits are provided between the high voltage withstanding amplifier and the resonance circuits correspondingly to the resonance circuits. Each of the high voltage withstanding analog switching circuits electrically connects/disconnects the high voltage withstanding amplifier to/from the corresponding resonance circuit. Since the reader/writer includes the high voltage withstanding analog switching circuits, there is no need to provide high voltage withstanding amplifiers at the previous stages of the resonance circuits as in a conventional reader/writer.

Abstract: A fully-static dual-voltage sense circuit designed for a mixed-voltage system senses the power-rail voltage of other devices that the device is interfaced with, and achieves a low-power consumption level without software assistance when the sensing circuit is active, and protects low-voltage process devices in the circuit from possible high voltage damage at the interface. In a preferred embodiment, the present invention includes an integrated circuit having a dual-voltage sense circuit, the sense circuit including a sense circuit input node supplied with an input voltage Vin; a sense circuit power input node supplied with a power-supply voltage; and a sense circuit output node outputting a digital signal of a voltage level equal to or less than the voltage level of a low-voltage digital signal, regardless of the voltage level of the input voltage.

Abstract: A multi-function output driver that may be used with at least two types of busses includes a multiplexer that shifts calibration bits to the pull-down transistors. This shifting changes which transistors of the transistor array are turned on when the pull-down drive transistors are driving. By changing which transistors are turned on, the impedance of the driver is changed. This shifting is used with a disable function on the pull-up drive-transistors to allow the driver to be used as an end-of-line termination, an open-drain driver, or as a source-terminated driver.

Abstract: A circuit for addressing leakage. The circuit may have a variable supply stage having an active load in parallel with a switch transistor where the active load and the switch transistor are coupled to a decoupling capacitor. The circuit may also have a leakage detect stage having a leak device coupled to a critical node. An embodiment of the circuit may have a supply node; an input node; an output node; a buffer stage where the buffer stage supply node is coupled to a variable supply stage output, the buffer stage input is coupled to the input node and the buffer stage output is coupled to the output node; a leakage detect stage where the leakage detect stage supply node is coupled to the supply node and the leakage detect stage input is coupled to the input node; and a variable supply stage where the variable supply stage supply node is coupled to the supply node and the variable supply stage input is coupled to the leakage detect stage output.

Abstract: A signal transition accelerating driver circuit for driving a signal line in the presence of an enable signal of a high level and to a potential level on the signal line for accelerating the potential change on the signal line in the presence of the enable signal of the low level, the signal transition accelerating driver circuit has a timer for determining an end point of the acceleration, thereby accurately defining a time period for accelerating the potential change.

Abstract: This is a driver circuit 100 for use in an integrated circuit 10 for driving two complimentary signals on output terminals 104 and 106. A single device, such as a Schottky diode 170, prevents voltage breakdown resulting from an externally supplied voltage on either output terminal 104, 106. The single device, such as Schottky diode 170, provides voltage breakdown protection for an output transistor 150 and a complimentary output transistor 152.The single device can be made larger than if two devices were used so that a voltage drop across the device resulting from normal forward current conduction is minimized.

Abstract: The data bus interface apparatus (243) which interfaces between one of a plurality of peripheral units (111) and a data bus (109). The data bus interface driver (243) is capable of biasing data to the voltage level of the data bus (109), accepting data signals (233) having different amplitudes and is immune to differences in ground voltage potentials caused by induced noise and differing environmental conditions. The data bus interface driver (243) is capable of data transition rates in excess of 1 MHz and has low EMI and RFI emissions.

Abstract: A parallel port interface for utilization between a first device and a second device designated by a user for transmitting a digital signal from the device to the second device. The parallel port interface includes a switchable driver circuit for transmitting the digital signal, which includes a first circuit for emulating an open collector circuit and a second circuit for emulating a totem pole circuit. The switchable driver circuit is controlled by a logic control circuit that automatically selects either the first circuit or the second circuit for transmitting the digital signal in response to the digital signal and a designation of the second device.

Abstract: An amplification-type photoelectric conversion device utilizes a JFET and is capable of amplifying charges generated by photoelectric conversion with a high amplification factor and improves the S/N ratio. The device is provided with a drive circuit for respectively applying driving signals to a source region, a drain region and a gate electrode of the JFET. The drive circuit has a first signal mode for accumulating charges generated by incident light on the JFET, and a second signal mode for causing the flow of current between the source and the drain and raising a potential difference between the source and the drain to a high level thereby causing an impact-ionization effect corresponding to an amount of the charges accumulated by the first mode to accumulate the resulting charges. A signal output corresponding to a total amount of the charges accumulated by the first and second modes is delivered from the drain.

Abstract: A row decoder for a semiconductor memory device is disclosed which includes a plurality of decoding circuits each driving a corresponding one of word lines in response to first and second control signals associated therewith. Each of the decoding circuits includes a first node supplied with the first control signal, a second node supplied with the second control signal, a first transistor connected between the first node and the corresponding word line and turned ON when the second control signal takes an active level, and a second transistor connected between the corresponding word line and a reference potential terminal and turned ON when the second control signal takes an inactive level.

Abstract: A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.

Abstract: An output driver and method including an output pad, for performing write operations from a central processor unit to a cache memory. The driver includes a pull-up circuit electrically connected to the output pad for switching the pad to a first logic state and a pull-down circuit electrically connected to the output pad for switching it to a second logic state. A plurality of signals are input to the pull-up and pull-down circuits to perform the switching of the output pad at integer and integer and a half clock cycles.

Abstract: A device-implemented method for driving a ferrimagnetic load (10), such as a phase shifter in an antenna array, which precisely meters the amount of magnetic flux imparted to the load (10) by sensing the voltage applied to a winding and integrating the sensed voltage over time. The time intergrated voltage is proportional to the magnetic flux imparted to the load (10) and is constantly compared to a preprogrammed value stored in a memory (18). When the sensed voltage reaches the preprogrammed value, the voltage is removed from the load (10) so that a metered amount of magnetic flux, proportional to the preprogrammed value, remains in the load (10). The load (10) is initially reset by delivering current in one direction through its winding until saturation is reached. The load (10) is set with a metered amount of magnetic flux by delivering current in the opposite direction through the winding.

Abstract: A read head for a Wiegand wire has an E-core with a pick-up coil for the "1" bit wound on one outer leg and a separate pick-up coil for the "0" bit wound on a second outer leg. The E-core is composed of a relatively thin ferromagnetic E-laminae spaced from a relatively thick E-laminae. Between thin and thick laminae in each leg there is an appropriately polarized magnet. The result is to establish a first field across the face of the read head between the center leg and a first outer leg. This first field reads the one bits. Similarly, a second field between the center leg and the other outer leg reads the zero bits. Each one bit wire is on one side of the code strip and each zero bit wire is on the other side of the code strip so that the one bit and zero bit wires are passed respectively across the first and second reading fields provided by the read head.

Abstract: A fail-safe electronic coincidence detecting circuit including a multiple winding saturable core reactor having a first and a second input winding and an output winding. An NPN transistor amplifier supplying a first pulse train to the first input winding and a PNP transistor amplifier supplying a second pulse train to the second input winding. The output winding producing signal pulses only when the first and second pulse trains are in synchronism.

Abstract: A rotating flux transformer which includes a magnetic core having poloidal primary and secondary windings and toroidal primary and secondary windings. Quadrature flux is produced in the magnetic core by connecting one end of the poloidal primary winding to the center of the toroidal primary winding. The quadrature flux combines vectorially to produce a rotating induction vector in the magnetic core.

Abstract: A monolithically integratable control circuit for switching inductive loads, comprising a Darlington-type final stage, is described. The base of the Darlington control transistor is coupled to the collector of a transistor for extracting charge, the transistor conducting in phase opposition to the Darlington control transistor. The emitter of the transistor for extracting charge is coupled to the negative supply terminal and to the output terminal of the final stage, via a first and a second diode respectively.