Abstract: Disclosed is a method for reducing the electromagnetic interference produced during the switching to the on state of a transistor for switching a quasi-resonant DC-DC voltage converter. The method includes the steps of: the transistor being initially controlled so as to be in the on state on the basis of a first control current, controlling the driving module by way of the control module so that the driving module switches the transistor to the off state at a first instant; and triggering the timer from the first instant, and, if the timer reaches a predefined duration threshold, controlling, by means of the driving module, the transistor so as to be in the on state on the basis of a second control current the intensity of which is lower than the intensity of the first control current.

Abstract: A control circuit includes: a power supply module, arranged to generate an output power to control an operation mode of a lighting device according to a control signal and a supply power; a switching module, coupled to the supply power, for selectively generating a first voltage signal of the supply power; and a signal controlling module, coupled between the switching module and the power supply module, for generating the control signal according to the first voltage signal.

Abstract: A gas flow measuring circuit includes at least one reference resistor and at least one variable resistor that varies in accordance with the characteristics of the flow of a gas and means for determination of the difference between the reference resistor and variable resistor, with at least one current loop arrangement including first current source means coupled in series with said reference resistor and second current source means coupled in series with said variable resistor wherein both resistors are connected to ground for providing an ideally constant current through the respective resistor to produce first voltages across the reference resistor and second voltages across the variable resistor, and voltage measuring means for measuring the voltage difference between said reference resistor and said variable resistor to produce a characteristic voltage difference representative of the characteristics of the gas.

Abstract: A power converter can include: first and second terminals; N A-type switching power stage circuits, each having a first energy storage element, where N is a positive integer, a first terminal of a first A-type switching power stage circuit in the N A-type switching power stage circuits is coupled to the first terminal of the power converter, and a second terminal of each of the N A-type switching power stage circuits is coupled to the second terminal of the power converter; one B-type switching power stage circuit; and N second energy storage elements, each being coupled to one of the N A-type switching power stage circuits, and the B-type switching power stage circuit is coupled between a terminal of one of the N second energy storage elements corresponding to the B-type switching power stage circuit and the second terminal of the power converter.

Abstract: An emulated peak current mode control (EPCMC) synchronous buck converter device is provided, and may include a converter having an inductor, a high-side switch, and a low-side switch, and an EPCM controller. The controller may include a PWM latch to alternately turn on and off the high-side and low-side switches, a current sense element to output a current sense voltage based on the inductor current, and a feedforward circuit to generate a feedforward voltage. The current sense element outputs a first current sense voltage while the low-side switch is turned on, and outputs a second current sense voltage while the low-side switch is turned off. The feedforward voltage is generated based on a voltage differential that represents a difference between the first current sense voltage and the second current sense voltage, and the PWM latch alternately turns on and off the high-side and low-side switches based on the feedforward voltage.

Abstract: A switching regulator with improved load regulation is discussed. The switching regulator increases an on time length of a first power switch if the switching regulator operates at discontinuous current mode and a current flowing through the second power switch crosses a zero reference, until the first power switch is turned on again; and the switching regulator maintains the on time length of the first power switch during other time period.

Abstract: A voltage regulator includes a first control circuit and a first voltage adjusting circuit. The first control circuit receives an output voltage and generates a first control signal according to the output signal. The first voltage adjusting circuit is coupled to the first control circuit, receives the first control signal, and adjusts the output voltage according to the first control signal.

Abstract: Provided is a switching power supply device capable of easily realizing multi-phase operation and current balancing with the number of operation phases depending on the amount of load.

Abstract: An on-chip low-voltage current sensing circuit for measuring current in an integrated circuit (IC). In one embodiment, an IC formed on a substrate, which includes a plurality of subcircuits, and a plurality of sensing circuits coupled to the plurality of subcircuits, respectively. The plurality of sensing circuits are configured to generate a plurality of currents, respectively, that are proportional to a plurality of load currents, respectively, consumed by the plurality of subcircuits, respectively, during operation thereof. A circuit is coupled to the plurality of sensing circuits and configured to generate a signal based on an aggregate of the plurality of currents.

Abstract: A circuit is operated by receiving an input reference signal at an input node, determining a scaling ratio based on the input reference signal, generating a digital input signal as a function of the determined scaling ratio, converting the digital input signal into an analog signal that is a scaled replica of the input reference signal, and providing the analog signal at an output node of the circuit and then, after a duration of time, coupling the input reference signal to the output node.

Abstract: A multiphase switching converter has a plurality of switching circuits coupled in parallel, and a plurality of control circuits configured in a daisy chain. Each control circuit receives a phase input signal, and provides a phase output signal and a switching control signal for controlling a corresponding switching circuit. One of the plurality of control circuits is master control circuit to provide the phase output signal and the switching control signal based on a turn-on control signal and the phase input signal. When a combination of the phase output signal and the switching control signal provided by the master control circuit meets a phase transfer type, the phase output signal of the master control circuit equals the turn-on control signal.

Abstract: A multi-phase power supply includes a plurality of phase controllers each driving a first terminal of a respective inductor alternatively between an input voltage and a ground voltage to regulate an output voltage in a work mode, keeping the first terminal of the respective inductor in a high impedance state during a non-work mode, having an input for receiving an enable signal for selecting between the work mode and the non-work mode, and generating a current monitor signal to represent a current through the respective inductor during both the work mode and the non-work mode, and a controller coupled to each phase controller for selectively enabling respective ones of the phase controllers in response to a load demand, receiving the current monitor signal from each phase controller, and selectively shutting down the multi-phase power supply when a total of current monitor signals from the phase controller exceeds a threshold.

Abstract: A method controls a boost converter having N switching cells using synchronous pulse width modulation, in which N is a natural integer that does not equal zero. The method includes: measuring input voltages and output voltages of the boost converter; determining an output vector to define a representation of a linear state of the boost converter; calculating the variation in power of the electrical load; determining the N duty factors as a function of the second derivative of the output vector, the derivative of the power of the electrical load, and the ratio between the input voltage and the output voltage that have been measured; and controlling each switching cell of the converter depending on the duty factor that has been determined.

Abstract: A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.

Abstract: A controller controls a circuit that provides a variable current to a load and provides a constant voltage to the load. The controller controls switches to adaptively respond to a change in a load current by transitioning into or out of pulse-skipping mode.

Abstract: A method for regulating a power conditioner output voltage level includes monitoring a first voltage level of a first supply source and a second voltage level of a second supply source and, while the power conditioner is being supplied by the first supply source, controlling a duty-cycle of an output switch of the power conditioner with feedback-based control signals generated based on errors between a target voltage level and samples of the output voltage level obtained at an output voltage sampling frequency. The method also includes, controlling, for a period corresponding to the output voltage sampling frequency, the duty-cycle of the output switch with an estimated control signal. The method also includes, while the power conditioner is being supplied by the second supply source, controlling the duty-cycle of the output switch using the feedback-based control signals.

Abstract: A fault protection method used in a multiphase switching converter which includes a plurality of switching circuits coupled in parallel and a plurality of control circuits configured in a daisy chain. Each control circuit has a first terminal coupled to a phase control signal, a second terminal coupled to a previous control circuit in the daisy chain to receive a phase input signal, and a third terminal coupled to a latter control circuit in the daisy chain to provide a phase output signal.

Abstract: A current monitor includes current sense logic and a processor. The current sense logic senses inductor current at a predetermined time point during operation of a constant on-time regulator. The processor determines output current of the constant on-time regulator based on the inductor current sensed at the predetermined time point. The predetermined time point corresponds to half of an on-time period of the constant on-time regulator. The output current may be determined during continuous conduction mode (CCM) or discontinuous conduction mode (DCM). During DCM mode, the processor determines the output current of the constant on-time regulator based on a skip time.

Abstract: A power supply circuitry includes a first transistor, a feedback circuit, a first differential amplifier circuit, a second differential amplifier circuit, and a first control circuit. The first transistor outputs a power supply voltage based on a drive signal. The feedback circuit generates a feedback voltage of the power supply voltage. The first differential amplifier circuit amplifies a difference between the feedback voltage and a reference voltage, and outputs the drive signal. The second differential amplifier circuit amplifies a difference between the reference voltage and the feedback voltage. The first control circuit detects a change in the power supply voltage by using a differentiation circuit and controls the power supply voltage based on an output of the second differential amplifier circuit.

Abstract: A COT (constant on-time) buck converter includes a first transistor, a second transistor, a driver circuit, an inductor, a first resistor, a second resistor, a capacitor, a load, and a feedback loop circuit. The feedback loop circuit includes a first switch, a second switch, an error amplifier, a comparator, a frequency locked loop circuit, an inverter and a COT logic circuit. The COT buck converter is able to improve DC (direct-current) regulation efficiency and transient response time.

Abstract: A voltage converting apparatus includes a comparison circuit, a compensation signal generator, and a voltage converter. The comparison circuit generates a comparison result according to an output voltage, an input voltage, and a compensated feedback signal. The compensation signal generator provides a compensation signal held to be equal to a reference voltage at a first time interval in an enable period in a working cycle and sets the compensation signal to be a ramp signal at a second time interval in the enable period. The compensation signal generator generates the compensated feedback signal according to a feedback signal and the compensation signal. The voltage converter generates a control signal according to the comparison result, performs a voltage converting operation through an inductor according to the control signal, and generates the output voltage. The feedback signal is generated according to a current on the inductor.

Abstract: A fault detection method is sampling currents flowing through a plurality of switching circuits to generate a plurality of current sampling signals, generating a first reference signal and a second reference signal based on a predetermined reference signal and a ripple threshold signal, and generating a plurality of fault signals based on comparison results of each of the plurality of current sampling signals with the first reference signal and the second reference signal. When one of the plurality of current sampling signals is between the first reference signal and the second reference signal, a corresponding one of the plurality of fault signals changes to a first state, and when the corresponding one of the plurality of fault signals remains the first state for more than a predetermined time period, a corresponding one of control signals turns off a corresponding one of the plurality of switching circuits.

Abstract: An alternating-current (AC)—direct-current (DC) power supply includes a circuit board including an alternating-current input terminal to which an alternating current is input and a direct-current output terminal from which a direct current is output. The AC-DC power supply includes a diode bridge that rectifies the alternating current input via the alternating-current input terminal, an alternating-current input line that electrically connects the alternating-current input terminal and the diode bridge, a coil connected to the diode bridge, a diode connected to the direct-current output terminal, a switching line that electrically connects the coil and the diode, and a switching element connected to the switching line. A portion of the switching line is disposed at right angles to a portion of the alternating-current input line.

Abstract: Embodiments described herein provide a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter. The ZCD includes a ZCD integrator configured to receive a switch voltage and an output voltage of a power stage of the DC-DC converter and to generate a zero-crossing detect signal based, at least in part, on the received switch voltage and output voltage, where the zero-crossing detect signal is configured to indicate an output current in an output inductor of the power stage of the DC-DC converter is approximately zero. The ZCD may also include a ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage, where the ZCD integrator is configured to generate the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.

Abstract: An apparatus includes a four-switch power converter having input terminals coupled to a power source and output terminals coupled to a capacitor, wherein the capacitor is connected in series with the power source, and a common node of the capacitor and the power source is connected to one input terminal of the four-switch power converter.

Abstract: A method may include operating a DC-DC switch converter in a forced continuous conduction mode in which for each switching cycle of the switch converter during the forced continuous conduction mode, the switch converter operates in a series of phases including: a first phase in which an inductor current flowing in an inductor of the switch converter increases from zero to a controlled positive current magnitude with respect to a first terminal and a second terminal of the inductor; a second phase in which the inductor current decreases from the controlled positive current magnitude to approximately zero; a third phase in which the inductor current decreases from approximately zero to a controlled negative current magnitude with respect to a first terminal and a second terminal of the inductor; and a fourth phase in which the inductor current increases from the controlled negative current magnitude to approximately zero.

Abstract: One or more embodiments relate to a reference voltage control circuit for a buck-boost converter. According to certain aspects, embodiments can increase or decrease the reference voltage for an error amplifier for controlling a pulse width modulation (PWM) signal when there is a change in the mode of operation. In these and other embodiments, the reference voltage control circuit is configured to modify the reference voltage by increasing or decreasing the reference voltage when there is a change in the mode of operation, so as to reduce overshoot or undershoot disturbances in the regulated output voltage during such transitions.

Abstract: A dc/dc buck converter controller comprises an artificial neural network (ANN) controller comprising an input layer and an output layer. The input layer receives an error value of a dc/dc buck converter and an integral of the error value. The output layer produces an output error voltage. A pulse-width-modulation (PWM) sliding mode controller (SMC) is configured to receive the output error voltage and produce a control action voltage by multiplying the output error voltage with a PWM gain. A drive circuit is configured to receive the control action voltage and provide a drive voltage to an input switch of the dc/dc buck converter. A PI control block is configured to modify a reference output voltage based on a maximum current constraint input. A locking circuit is configured to maintains the output error voltage at the saturation limit of the PWM SMC to manage a maximum duty cycle constraint.

Abstract: A method includes driving a first transistor to conduct a first current into an inductor when conductive and driving a second transistor to conduct a second current into the inductor when conductive. A first sense current is generated in response to the first current and a copy of the second current. A second sense current is generated in response to the second current and a copy of the first current. The first sense current is adjusted in response to the copy of the second current when the first transistor is nonconductive. The second sense current is adjusted in response to the copy of the first current when the second transistor is nonconductive. On times of the first and second transistors are controlled in response to a sum of the first and second sense currents.

Abstract: Methods, systems, and devices for techniques for adjusting current based on operating parameters are described. An apparatus may include an amplifier, a feedback component, and first and second current generators. The amplifier may include an input for receiving a first voltage and an output for outputting a second voltage. The first current generator may be coupled with the output of the amplifier and generate a first current based at least in part on the second voltage. The feedback component may be coupled with the first current generator to modify the first current based at least in part on an operating temperature associated with a memory device. The first current may be proportional to the operating temperature. The second current generator may be coupled with the first current generator to generate a second current based at least in part on the first current modified by the feedback component.

Abstract: Receiver circuitry to convert a pulse-width-modulated (PWM) signal into a digital data signal includes analog-to-digital converter circuitry that converts the PWM signal into an intermediate signal, a timing generator that derives control signals from the intermediate signal, analog charge storage circuitry that is charged and discharged according to the control signals, and circuitry that derives a digital output signal from an analog waveform output by the charge storage circuitry. The charge storage circuitry includes a capacitance and a current-limiting element, one of which is variable to control a time constant of the charge storage circuitry for calibration to a data rate of the PWM signal. A control signal may be single-ended and compared to a threshold, or may be differential with the legs compared to each other. The output is derived on a falling clock edge, and maintained until a subsequent falling clock edge.

Abstract: Techniques are described to slow the turn off of a pass transistor coupled to an inductive load and being controlled by a hot swap or switch controller in the event of a fault on the load side. Active circuitry can control the gate of the pass transistor, e.g., field-effect transistor (FET), as the inductive load de-energizes and a feedback loop can servo the gate voltage of the pass transistor in order to ensure that its source does not go below a reference voltage.

Abstract: An optical communication system includes a light source and an output capacitor coupled to the light source. The system also includes a switching converter circuit coupled to the output capacitor. The switching converter circuit is configured to provide an output voltage to the output capacitor based on an active mode and a power-save mode. The switching converter circuit includes a controller configured to perform pulse gating in the power-save mode based on a timer and a comparison of the output voltage with a voltage threshold.

Abstract: A switching regulator having a low start-up voltage includes a power stage and a switch control circuit. The switch control circuit includes a power control switch. The power control switch is formed by a low threshold voltage transistor having a first conductivity type in a semiconductor substrate. The low threshold voltage transistor having the first conductivity type includes a first lightly doped region having a second conductivity type which forms a channel region of the low threshold voltage transistor having the first conductivity type. The semiconductor substrate includes a second lightly doped region having the second conductivity type which is formed by a same manufacturing process as the first lightly doped region having the second conductivity type. The second lightly doped region having the second conductivity type forms adrift region of a high-voltage transistor having the second conductivity type in the semiconductor substrate.

Abstract: A semiconductor device includes an analog-digital conversion circuit that converts a voltage at a node between a reference resistor and a sensor resistor into output data, the reference resistor and the sensor resistor being connected in series. The semiconductor device calculates a resistance value of the sensor resistor using a first output data obtained in a first conversion phase and second output data obtained in a second conversion phase. In the first conversion phase, a high potential side voltage is applied to one end of the reference resistor and a low potential side voltage is applied to one end of the sensor resistor. In the second conversion phase, the low potential side voltage is applied to one end of the reference resistor and the high potential side voltage is applied to one end of the sensor resistor.

Abstract: An apparatus for efficiently driving visual displays via light-emitting devices may include (1) at least one light-emitting device, (2) a buck driver circuit electrically coupled to the light-emitting device, wherein the buck driver circuit includes an inductor, and (3) a boost circuit electrically coupled between the buck driver circuit and a power source, wherein the boost circuit includes an additional inductor. Various other apparatuses, systems, and methods are also disclosed.

Abstract: An information handling system includes a power assist unit (PAU) and a baseboard management controller (BMC). The PAU is coupled to a power rail and includes a power storage element, a converter coupled to the power storage element and the power rail, and a controller. The controller receives a current level indication indicating a current provided to a load of the information handling system, directs the converter to provide power from the power storage element to the power rail when the current level indication is greater than a threshold level, directs the converter charge the power storage element from the power rail when the current level indication is greater than the threshold level, and provides a charge level indication that indicates an amount of charge on the power storage unit. The BMC receives the charge level indication, and sets a peak power limit for the information handling system based on the charge level indication.

Abstract: The present embodiments allow multiphase buck controllers to be able to detect Power-on-Reset (POR) automatically and subsequently reboot the system and reconfigure the system as a single or multi-rail system. Some embodiments use an onboard bus that can communicate between controllers. In these and other embodiments, the system is able to recover automatically from a power failure afflicting any or all of the controllers. Embodiments are applicable to flexible plug-and-play modular digital buck regulation applications.

Abstract: The present disclosure relates to a controller for controlling operation of at least first and second traction machines in a vehicle. The controller includes a processor configured to predict an operating temperature of each of said at least first and second traction machines for at least a portion of a current route. The processor determines at least first and second torque requests for said at least first and second traction machines. The at least first and second torque requests are determined in dependence on the predicted operating temperatures of the at least first and second traction machines. The processor generates at least first and second traction motor control signals in dependence on the determined at least first and second torque requests. The present disclosure also relates to method of controlling at least first and second traction machines in a vehicle.

Abstract: A charge sharing circuit includes a charge source having an accumulated first charge and a charge load having an accumulated second charge, where during a charge sharing interval the second charge is less than the first charge. A charge sharing regulator selectively couples between the charge source and the charge load along a charge sharing path. The charge sharing regulator regulates transfer of a shared amount of charge from the charge source to the charge load during the charge sharing interval.

Abstract: A buck converter includes a power switch having a first end to receive an input voltage, a synchronous switch connected between a second end of the power switch and the ground, an inductor having a first end connected to the other end of the power switch, and a switch control circuit configured to turn off the synchronous switch when a zero voltage delay time passes after an inductor current flowing through the inductor reaches a predetermined reference value, calculate a dead time based on the input voltage and the zero voltage delay time, and turn on the power switch when the dead time passes following the turn-off time of the synchronous switch.

Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output DC voltage with controlled ripple current. The buck converter may include one or more main buck converter stages with coupled outputs and one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents at the coupled outputs to cancel ripple currents generated in the one or main buck converter stages. Each of the one or more main buck converter stages and each of the one or more suppression buck converter stages may include a stacked transistor pair with an inductor at an output. A drain terminal of one transistor of each transistor pair in the one or more main buck converter stages may be biased at a first supply voltage.

Abstract: A voltage converting apparatus is provided. A control circuit connects a disturbance element to a voltage-dividing resistor network to disturb a feedback voltage and generate a detection voltage during a resistance detection period, and determines whether the voltage-dividing resistor network is aging according to the detection voltage.

Abstract: A power converter circuit that includes a switch circuit, and multiple phase and amplifier circuits, may generate a voltage level on a regulated power supply node of a computer system. The amplifier circuits may generate respective demand currents using a voltage level of the regulated power supply node and a reference voltage. In response to activation of a multi-phase operating mode, the switch circuit may short the outputs of the amplifier circuits to generate a common demand current. The multiple phase circuits may sequentially source current to regulated power supply node using the common demand current.

Abstract: Aspects of the disclosure provide for a circuit. In an example, the circuit includes an input circuit having a first output and a second output, a first timer having a first input coupled to the first output of the input circuit, a second timer having a first input coupled to the second output of the input circuit, a second input coupled to an output of the first timer, and an output coupled to a second input of the first timer, and an output circuit coupled to the output of the first timer and the output of the second timer.

Abstract: A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.

Abstract: According to certain aspects, a predictive tracking scheme is provided for sampling inductor currents in a digital PWM controller used for high-bandwidth voltage regulation. In one or more embodiments, the predicted current derived from the PWM waveform is fed forward to the current sense ADC in order to reduce the required conversion range. These and other embodiments only need to convert a few of the LSB of the ADC in order to correct the largest error expected in the synthesizer.

Abstract: Voltage converter having light-load control. In some embodiments, a voltage converter can be configured to receive an input voltage and generate a regulated voltage. Such a voltage converter can include a determining unit configured to determine whether the voltage converter is in a first load state. The voltage converter can further include a driving unit in communication with the determining unit, and be configured to generate a first driving signal when the voltage converter is in the first load state. The voltage converter can further include a switching unit in communication with the driving unit, and be configured to route the first driving signal to a control element of the voltage converter when the voltage converter is in the first load state, and be further configured to route a second driving signal to the control element when the voltage converter is in a second load state.

Abstract: A power supply apparatus that can realize ripple reduction, and an electronic control unit including the power supply apparatus are provided. In view of this, a PWM controller generates a PWM signal, and a PFM controller generates a PFM signal having a phase independent of the PWM signal. A level-fixed period generating circuit sets a level-fixed period having a start timing at a selection timing set to an edge of the PFM signal. A mode selecting circuit selects, at the selection timing and as a switching control signal, the PWM signal instead of the PFM signal, and controls a logic level of the switching control signal in the level-fixed period starting at the selection timing, such that the logic level becomes a fixed logic level.

Abstract: Circuits and methods for minimizing charge losses due to negative transient voltage at summing terminals of an analog to digital converter (ADC) are disclosed. The ADC is coupled to a multi-bit digital to analog converter (DAC) at the summing terminals. The ADC and the DAC include PMOS and NMOS transistors whose timing are controlled to reduce charge losses. The PMOS transistors are turned ON before the NMOS transistors. Also, the PMOS transistor of the ADC is turned ON at a slower rate than the PMOS transistors of the DAC.