Abstract: In a method and system for identifying addresses of slave devices, the system includes a main board, slave devices, and a power source. The main board is electrically connected to the slave devices and a delay unit is set in each slave device. An output terminal of the delay unit is electrically connected to the main board. The delay unit outputs a delay signal to the main board when first powered on, the main board receives the delay signal, computes a delay time of the delay signal, and by reference to a preset table identifies the slave device based on the specific delay time. Occupation of input and output I/O pins is reduced, a device for identifying addresses of slave devices is also disclosed.

Abstract: A stacked semiconductor device includes: a plurality of semiconductor chips that are stacked in a vertical direction, wherein each of the semiconductor chips includes: a plurality of first through-electrodes; a plurality of second through-electrodes positioned adjacent to the first through-electrodes; a first voltage driving circuit suitable for providing the first through-electrodes with a test voltage or a ground voltage based on a first driving control signal; a second voltage driving circuit suitable for providing the second through-electrodes with the test voltage or the ground voltage based on a second driving control signal; and a failure detection circuit suitable for generating a failure signal based on a plurality of first detection signals received through the first through-electrodes and a plurality of second detection signals received through the second through-electrodes.

Abstract: A microelectronic device that includes a sensor die, compute fabric dies, and storage component dies. Each compute fabric die has processing circuit components and data storage circuit components. A circuit component is selected and identifying information is generated by changing biasing and control parameters of the selected circuit component.

Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.

Abstract: In accordance with an embodiment of the present invention, there is provided a circulation method of a test tray in a test handler, the method comprising: in case of a first mode of test of temperature condition, firstly circulating the test tray along a first circulation path; and in case of a second mode of test of temperature condition different from the first mode, secondly circulating the test tray along a second circulation path, wherein the first circulation path and the second circulation path are different from each other in the transfer direction of the test tray at least in some sections.

Abstract: Toggling functional critical path timing sensors measure delays in toggling functional critical paths that are replicas of actual critical paths or representations of worst-case delay paths. A Toggle flip-flop or Linear-Feedback-Shift Register (LFSR) drives high-transition-density test patterns to the toggling functional critical paths. When a toggling functional critical path's delay fails to meet set-up timing requirement to a next register, the toggling functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. A margin delay buffer adds a delay to the toggling functional critical path before being clocked into an early capture flip-flop. A reference register receives the test pattern without the delay of the toggling functional critical path, and an exclusive-OR (XOR) gate compares outputs of reference and early capture flip-flops to generate timing failure signals to the controller.

Abstract: Toggling functional critical path timing sensors measure delays in toggling functional critical paths that continuously receive patterns from an aging pattern generator. Wear is accelerated. A margin delay adjustment controller sweeps margin delays until failures occur to measure delays. The margin delay is then adjusted in functional critical path timing sensors that add the margin delay to functional critical paths that carry user data or chip controls during normal operation. When the path delays fail to meet requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. Wear on the toggling functional critical paths is accelerated using both toggle and low-transition-density patterns. Circuit aging is compensated for by increasing margin delays to timing sensors.

Abstract: A test system for testing electrostatic testers, is used to test at least one electrostatic tester each including a voltage test terminal and a connection test terminal. The test system includes at least one optical coupler circuit and a chip. Each optical coupler circuit is coupled the voltage test terminal and the connection test terminal of one corresponding electrostatic tester, and each optical coupler circuit converts voltages of the voltage test terminal and the connection test terminal respectively to a voltage test signal and a connection test signal. The chip is couple to the at least one optical coupler circuit, and receives the connection test signal and the voltage test signal produced by the at least one optical coupler circuit, and determines whether the corresponding electrostatic tester connected to each optical coupler circuit is worked normally according to the connection test signal and the voltage test signal.

Abstract: An integrated circuit comprising N adjacent identical blocks indexed by index j, a current block connected to preceding and following blocks, each comprising identification circuits comprises: N ordered inputs indexed i, connected to N outputs of the preceding block of same index; and N ordered outputs indexed i, connected to N inputs of the following block of same index; each input for i?N of the current block connected by routing line indexed to output i+1 of the current block; last input N of the current block not connected to output of the current block; and first output 1 of the current block not connected to input of the current block; each block comprising: a connection pad; and N logic gates indexed i, each gate comprising first and second inputs and an output, N buses indexed i comprising a line through N blocks, and connected to output of a logic gate.

Abstract: A test circuit of a semiconductor apparatus may include a period signal counting block configured to count a period signal by a predetermined number of times, and enable an overflow signal. The test circuit of the semiconductor apparatus may include a clock signal counting block configured to count an internal clock signal until the overflow signal is enabled, and may output clock counting codes. The test circuit of the semiconductor apparatus may include an update register configured to receive and store the clock counting codes based on the overflow signal.

Abstract: An integrated circuit is disclosed. The integrated circuit includes input and output pads, a first integrated circuit portion having first circuitry, and a second integrated circuit portion having second circuitry different from the first circuitry. The first integrated circuit portion is configured to provide an input test signal from the input pad to the second integrated circuit portion, and provide an output test signal from the second integrated circuit portion to the output pad, the output test signal being generated by second integrated circuit portion in response to the input test signal.

Abstract: An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.

Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.

Abstract: An integrated circuit device includes component devices (that include primary and alternate devices) and storage elements connected to the component devices. The storage elements store different sets of repair addresses indicating which of the primary devices and alternate devices are to be enabled. Further, a controller is connected to the storage elements, and a temperature sensor is connected to the controller. The temperature sensor senses the temperature. The controller selects one of the different storage elements to select at least one of the sets of repair addresses based on the temperature sensed by the temperature sensor. The sets of repair addresses share use of at least one of the alternate devices and at least one of the primary devices.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: Mechanisms are provided for chip (e.g., semiconductor chip) identification (e.g., low cost secure identification). In one example, a method of manufacturing for implementing integrated chip identification is provided. In another example, a method of using a chip with an integrated identification is provided.

Abstract: A semiconductor device and a test apparatus including the same, the semiconductor device including a command distributor receiving a serial command that is synchronized with a first clock signal and converting the serial command into a parallel command, a command decoder receiving the parallel command and generating a pattern sequence based on the parallel command, and a signal generator receiving the pattern sequence and generating operating signals synchronized with a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.

Abstract: This invention has an object of providing a semiconductor integrated circuit enabling further reduction of the number of test terminals without depending on a compression/expansion technique alone. The semiconductor integrated circuit of the invention is connected to a terminal group used to exchange test information of a circuit to be tested, and comprises a utilization device which utilizes, when reading a test result, a terminal subgroup of the terminal group, which is not used to transmit information required to read the test result, to receive the test result from the circuit to be tested.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: A system includes a microprocessor that executes microcode designed to query all or some of the electronic circuits that are on a device under test. The results of the query are written to an RFID IC register. The RFID IC is queried by an interrogator to obtain test results.

Abstract: Both a device-identification feature and a temperature-sensor feature are combined on a single integrated circuit. In various embodiments, both features are not operative simultaneously.

Abstract: An integrated circuit includes a device identification circuit and a temperature sensor diode connected in parallel from a common node. The device identification circuit includes a resistor connected to a diode-connected transistor. The device identification circuit and the temperature sensor diode are adapted to not be simultaneously operating in an ON state. A first voltage is applied to the common node to place the device identification circuit in an ON state and place the temperature sensor diode in an OFF state to identify the integrated circuit. A second voltage is applied to the common node to place the device identification circuit in an OFF state and place the temperature sensor diode in an ON state to determine a temperature of the integrated circuit.

Abstract: A system and method for testing remote controls. A number of remote controls are identified. The remote controls are received on a tray of a remote control tester. The tray is positioned for testing. The number of remote controls are tested within the tray utilizing the remote control tester in response to identifying the number of remote controls.

Abstract: A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.

Abstract: A sensor module includes a sensor, a cover, and a wiring unit. The cover holds the sensor and includes a connector configured to make a connection with an external device. The wiring unit is held by the cover, is arranged from the connector to the sensor, and includes a connecting member extending from the connector to a central region of the cover in its width direction, which is perpendicular to the central line, and a wiring member extending from the central region of the cover in its width direction to a vicinity of the sensor. The cover and connecting member are integrally formed from a mold material. The connecting member includes a first connecting terminal exposed from a surface of the mold material at the central region of the cover in its width direction. The wiring member includes a second connecting terminal conductively joined to the first connecting terminal.

Abstract: There is established an easier inspection method with which it is not required to set up probes on wires. Also, there is provided an inspection apparatus using this inspection method. With the inspection apparatus or inspection method, primary coils of an inspection substrate and secondary coils of a device substrate are superimposed on each other so that a certain space is maintained therebetween. An AC signal is inputted into the primary coils, thereby generating an electromotive force in each secondary coil by electromagnetic induction. Then, each circuit provided on the device substrate is driven using the electromotive force and information possessed by an electromagnetic wave or electric field generated in this circuit is monitored, thereby detecting each defective spot.

Abstract: The present disclosure provides a semiconductor device including: a semiconductor identifier holding portion configured to hold a semiconductor identifier for identifying a semiconductor device; and a control portion configured such that upon elapse of a predetermined time period following receipt of an externally input instruction to hold the semiconductor identifier, the control portion issues an instruction to the semiconductor device immediately downstream of the semiconductor device to hold a semiconductor identifier of the immediately downstream semiconductor device and that during the time period between the point in time at which the externally input instruction is received and the point in time at which the instruction is issued to the immediately downstream semiconductor device to hold the semiconductor identifier thereof, the control portion causes the semiconductor identifier holding portion to hold the externally input identifier.

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

Abstract: A cable with a wire disconnection detection function includes a detecting wire including a conductor formed by twisting a plurality of strands, and a detected wire including a conductor formed by twisting a plurality of the strands. A twist pitch of the conductor of the detecting wire is longer than that of the conductor of the detected wire.

Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

Abstract: A test method includes: generating a start command in responses to a user input; testing each of the electronic devices in responses to the start command, and generating a test result for each of the electronic devices; obtaining a unique identifier of each of the electronic devices; obtaining the test result of each electronic device and generating a test file corresponding to each of the electronic device to record the test result; naming the test file according to the unique identifier of the corresponding electronic device; obtaining the test files, identifying the test files according to the test file name and determining whether each of the electronic devices are running in a normal state by analyzing the test result recorded in the test file. A test device using the above method is also described.

Abstract: It is aimed to provide a probe card test system and a relay driving test method for probe cards which can automatically and continuously perform tests without bringing needle tips into contact with a number of relays mounted on a probe card and by using a device. In a probe card test system for testing a probe card using a tester, the probe card includes a substrate having a first probe and a first relay connected to the first probe, a relay controller for the first relay and a first measurement channel for connecting the first relay and the first probe to the tester are further provided on the substrate. The tester includes a DC power supply, a control board for controlling the relay controller for the first relay, and a first measurement circuit connected to the first measurement channel, the DC power supply and a voltmeter. The first measurement circuit includes a first resistor having a predetermined time constant and a first changeover switch to be connected to the first measurement channel.

Abstract: An apparatus comprising a multiplexer circuit, a plurality of bit generation circuits, and a control circuit. The multiplexer circuit may be configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal. The plurality of bit generation circuits may each be configured to generate one of the plurality of input bits. The control circuit may be configured to generate the control signal.

Abstract: Apparatus and methods for non-contact testing of electronic components printed on a substrate (3) are provided. Test circuits (11) are printed on the substrate (3) at the same time as the desired electronic component. The test circuits (11) are all optical and include a first portion (13) for providing electrical energy for the test circuit (11) and a second portion (15) for generating a detectable optical signal that is indicative of at least one electrical property of the electronic component. The test circuits are used in real time and minimize the production of unusable scrap in the printing of such products as ePaper.

Abstract: Multiple test pins receive, as input data, multiple data output from a DUT. Multiple multiplexers receive the multiple data input to the multiple test pins and selects one of the data thus input, and outputs the data thus selected. Multiple logical comparators are respectively provided for the multiple multiplexers and judge whether or not the data selected by the corresponding multiplexers match the expected values.

Abstract: A circuit board including a plurality of components; a plurality of light sources aligned along at least one axis; and a controller configured to activate the light sources to identify at least one of the components. The components on the circuit board can be identified by the light sources in response to a variety of conditions.

Abstract: A method and a system for qualifying an integrated circuit according to a parasitic supply peak detector that it contains, including: supply of the integrated circuit to be tested under at least a first voltage; checking of a starting of the circuit; application of at least one first noise peak on the circuit power supply, while respecting an amplitude and time gauge; and comparison of average currents consumed by the circuit before and after the peak.

Abstract: A probe head assembly for testing a device under test includes a plurality of test probes and a probe head structure. The probe head structure includes a guide plate and a template and supports a plurality of test probes that each includes a tip portion with a tip end for making electrical contact with a device under test, a curved compliant body portion and a tail portion with a tail end for making electrical contact with the space transformer. Embodiments of the invention include offsetting the position of the tail portions of the test probes with respect to the tip portions of the test probes so that the tip portions of the test probes are biased within the apertures of the guide plate, using hard stop features to help maintain the position of the test probes with respect to the guide plate and probe ramp features to improve scrubbing behavior.

Abstract: To prevent an excessive current from flowing through a device under test. A test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section that is provided in a path leading from the power supply section to the device under test; a first semiconductor switch that is provided in the path leading from the inductive load section to the device under test and is connected in parallel with the device under test; and a control section that turns the first semiconductor switch ON when supply of the power supply voltage to the device under test is stopped.

Abstract: A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.

Abstract: An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: A semiconductor device and a test apparatus including the same, the semiconductor device including a command distributor receiving a serial command that is synchronized with a first clock signal and converting the serial command into a parallel command, a command decoder receiving the parallel command and generating a pattern sequence based on the parallel command, and a signal generator receiving the pattern sequence and generating operating signals synchronized with a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.

Abstract: There is provided a waveform observing apparatus with a reduced depth in such a manner that the waveform observing apparatus is one including a terminal board, connecting wiring extending from external equipment, a memory for receiving measured data through the terminal board, to store the measured data, and a display for displaying the measured data in waveform, the apparatus including: a first intra-body substrate, installed in an erect state inside a body frame of the waveform observing apparatus; a plurality of first connectors, provided on the first intra-body substrate; and a measurement module, which is connector-connected to the first connector of the first intra-body substrate, to be installed between the first intra-body substrate and the terminal board, and also includes a measurement circuit, wherein a plurality of measurement modules are detachable in an aligned state with respect to the erect first intra-body substrate.

Abstract: A circuit with switchable functionality has a first integrated circuit, which has, in a first operating mode, full functionality and which has, in at least one other operating mode, a functionality which is reduced in comparison with the full functionality. The circuit further has an output terminal to which a coupling element can be coupled, an identification device which identifies whether a first supply potential has been applied to the output terminal via the coupling element and in this case produces a status signal with a first value and otherwise produces a status signal with a second value, a setting device, which sets the full or reduced functionality as a function of the value of the status signal in the first integrated circuit. The invention also relates to an electronic component having such a circuit arrangement.

Abstract: There is established an easier inspection method with which it is not required to set up probes on wires. Also, there is provided an inspection apparatus using this inspection method. With the inspection apparatus or inspection method, primary coils of an inspection substrate and secondary coils of a device substrate are superimposed on each other so that a certain space is maintained therebetween. An AC signal is inputted into the primary coils, thereby generating an electromotive force in each secondary coil by electromagnetic induction. Then, each circuit provided on the device substrate is driven using the electromotive force and information possessed by an electromagnetic wave or electric field generated in this circuit is monitored, thereby detecting each defective spot.

Abstract: An identification device for electronic circuits comprises at least two electronic components having different electronic characteristics, a detection unit configured to detect at least one electrical parameter determining the electronic characteristics of the electronic components and an evaluation unit configured to evaluate a mismatch exhibited by the at least two electronic components with respect to each other. In order to distinguish different electronic circuits, the at least one electrical parameter of the electronic components is detected by the detection unit and is analyzed by the evaluation unit.

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the rings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.