With Recording Of Test Result Patents (Class 324/754.19)
  • Patent number: 10176071
    Abstract: Methods and apparatus for performing event correlation using codebook processing including determining a most probable set of problems for observed symptoms in a system. In embodiments, a correlation matrix is received which has managed objects. Hypotheses are defined as a subset of problems having observed symptoms based on the correlation matrix and evaluated.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 8, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: David Ohsie, Cheuk Lam
  • Patent number: 8970239
    Abstract: An audit device according to one embodiment includes a substrate; at least one test element coupled to the substrate; a connector adapted for coupling the at least one test element to leads of a cable; and a probe for detecting at least one of: voltage across and current through the at least one test element. Additional systems and methods are also presented.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Myron H. Gentrup, Icko E. T. Iben, John T. Kinnear, Jr.
  • Publication number: 20140049280
    Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip.
    Type: Application
    Filed: December 19, 2012
    Publication date: February 20, 2014
    Applicant: SK hynix Inc.
    Inventor: Yeon Ok KIM
  • Patent number: 8639461
    Abstract: A circuit and method for digitizing jitter in a high speed digital signal receives a digital signal using a comparator and supplies a clock signal to a counter. The circuit and method determine the frequency of the digital signal using the clock signal and the counter, and calculate the period of the digital signal based on the frequency (using a logic element). The method and circuit provide a linearized delay for jitter analysis based on the period of the digital signal (using a delay shift circuit) and output a delayed digital signal from the digital signal based on the linearized delay (using a measure delay circuit). The circuit and method supply the digital signal and the delayed digital signal to a programmable unit. The programmable unit comprises flip flops. The circuit and method count transitions of the flip flops within the programmable unit using the counter. The flip flops transition when the digital signal differs from the delayed digital signal.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: John F. Sweeney, James Mallabar
  • Patent number: 8531197
    Abstract: An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: September 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yefim-Haim Fefer, Valery Neiman, Sergey Sofer
  • Patent number: 8159209
    Abstract: A digital signal delay measuring circuit for measuring a delay time of a digital signal of a scan-testable digital circuit inside a device to be tested is provided. The circuit includes: outputting means for outputting a delay time measuring signal as a digital signal; delay means for delaying a timing when a state of the delay time measuring signal is changed; and at least two signal holding means, each receiving the delay time measuring signal and holding the state of the delay time measuring signal at a holding-command input timing.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: April 17, 2012
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Kensuke Yamaoka
  • Publication number: 20120074978
    Abstract: An audit device according to one embodiment includes a substrate; at least one test element coupled to the substrate; a connector adapted for coupling the at least one test element to leads of a cable; and a probe for detecting at least one of: voltage across and current through the at least one test element. Additional systems and methods are also presented.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 29, 2012
    Applicant: International Business Machines Corporation
    Inventors: Myron H. GENTRUP, Icko E.T. IBEN, John T. KINNEAR, JR.
  • Patent number: 8121732
    Abstract: A target position detection apparatus for a robot includes: a robot including an arm configured to be freely moved in at least two directions of X and Y axes, the arm having a wrist axis provided at a distal end of the arm and configured to be freely moved in a horizontal direction, and the wrist axis being provided with an end effector; and a control unit adapted for driving a memory to store a teaching point therein and controlling an operation of the robot such that the end effector will be moved toward the teaching point stored in the memory.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: February 21, 2012
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Yasuhiko Hashimoto, Nobuyasu Shimomura, Takao Yamaguchi, Tetsuya Yoshida
  • Patent number: 8089293
    Abstract: A test and measurement instrument including a port including a plurality of connections; an impedance sense circuit configured to sense an impedance coupled to a connection of the plurality of connections; and a controller configured to setup the test and measurement instrument in response to a sensed impedance from the impedance sense circuit.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: January 3, 2012
    Assignee: Tektronix, Inc.
    Inventor: Michael S. Hagen
  • Patent number: 8022718
    Abstract: A method of inspecting an electrostatic chuck (ESC) is provided. The ESC has a dielectric support surface for a semiconductor wafer. The dielectric support surface is scanned with a Kelvin probe to obtain a surface potential map. The surface potential map is compared with a reference Kelvin probe surface potential map to determine if the ESC passes inspection.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: September 20, 2011
    Assignee: Lam Research Corporation
    Inventors: Armen Avoyan, Hong Shih, John Daugherty